Searched refs:am (Results 1 – 8 of 8) sorted by relevance
/qemu/target/mips/sysemu/ |
H A D | physaddr.c | 25 static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx) in is_seg_am_mapped() argument 65 if ((adetlb_mask << am) < 0) { in is_seg_am_mapped() 72 return ((adetlb_mask << am) < 0); in is_seg_am_mapped() 81 unsigned int am, bool eu, in get_seg_physical_address() argument 85 int mapped = is_seg_am_mapped(am, eu, mmu_idx); in get_seg_physical_address() 107 unsigned int am = (segctl & CP0SC_AM_MASK) >> CP0SC_AM; in get_segctl_physical_address() local 112 access_type, mmu_idx, am, eu, segmask, in get_segctl_physical_address() 177 unsigned int am = CP0SC_AM_UK; in get_physical_address() local 181 am = (env->CP0_SegCtl1 & CP0SC1_XAM_MASK) >> CP0SC1_XAM; in get_physical_address() 184 if (env->CP0_Status & am_ksux[am]) { in get_physical_address() [all …]
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/qemu/hw/misc/ |
H A D | mips_itu.c | 91 uint64_t *am = &tag->ITCAddressMap[0]; in itc_reconfigure() local 93 hwaddr address = am[0] & ITC_AM0_BASE_ADDRESS_MASK; in itc_reconfigure() 94 uint64_t size = (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK); in itc_reconfigure() 95 bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0; in itc_reconfigure() 110 uint64_t *am = &tag->ITCAddressMap[0]; in itc_tag_write() local 126 am_old = am[index]; in itc_tag_write() 127 am[index] = (data & mask) | (am_old & ~mask); in itc_tag_write() 128 if (am_old != am[index]) { in itc_tag_write()
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/qemu/target/hexagon/ |
H A D | gen_printinsn.py | 80 am = assign.match(t) 81 if am and len(am.group(0)) == me - ms:
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/qemu/hw/i386/ |
H A D | intel_iommu.c | 2200 hwaddr size = (1 << am) * VTD_PAGE_SIZE; in vtd_iotlb_page_invalidate_notify() 2243 trace_vtd_inv_desc_iotlb_pages(domain_id, addr, am); in vtd_iotlb_page_invalidate() 2245 assert(am <= VTD_MAMV); in vtd_iotlb_page_invalidate() 2248 info.mask = ~((1 << am) - 1); in vtd_iotlb_page_invalidate() 2265 uint8_t am; in vtd_iotlb_flush() local 2282 am = VTD_IVA_AM(addr); in vtd_iotlb_flush() 2284 if (am > VTD_MAMV) { in vtd_iotlb_flush() 2586 uint8_t am; in vtd_process_iotlb_desc() local 2610 am = VTD_INV_DESC_IOTLB_AM(inv_desc->hi); in vtd_process_iotlb_desc() 2611 if (am > VTD_MAMV) { in vtd_process_iotlb_desc() [all …]
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/qemu/docs/system/riscv/ |
H A D | virt.rst | 152 $ git am riscv.patch
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H A D | sifive_u.rst | 170 $ git am riscv.patch
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/qemu/target/i386/ |
H A D | cpu.c | 6140 X86CPUModel *am = g_new0(X86CPUModel, 1); in x86_register_cpudef_types() local 6141 am->cpudef = def; in x86_register_cpudef_types() 6142 am->version = vdef->version; in x86_register_cpudef_types() 6143 am->is_alias = true; in x86_register_cpudef_types() 6144 x86_register_cpu_model_type(vdef->alias, am); in x86_register_cpudef_types()
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/qemu/docs/devel/migration/ |
H A D | compatibility.rst | 36 I am going to list the number of combinations that we can have. Let's
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