Home
last modified time | relevance | path

Searched refs:ar (Results 1 – 25 of 64) sorted by relevance

123

/qemu/hw/acpi/
H A Dcore.c418 ar->tmr.update_sci(ar); in acpi_pm1_evt_power_down()
424 ar->pm1.evt.sts = 0; in acpi_pm1_evt_reset()
425 ar->pm1.evt.en = 0; in acpi_pm1_evt_reset()
450 ar->pm1.evt.update_sci(ar); in acpi_pm_evt_write()
454 ar->pm1.evt.update_sci(ar); in acpi_pm_evt_write()
515 ar->tmr.update_sci(ar); in acpi_pm_tmr_timer()
542 ar->tmr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, acpi_pm_tmr_timer, ar); in acpi_pm_tmr_init()
656 ar->gpe.len = len; in acpi_gpe_init()
667 memset(ar->gpe.sts, 0, ar->gpe.len / 2); in acpi_gpe_reset()
668 memset(ar->gpe.en, 0, ar->gpe.len / 2); in acpi_gpe_reset()
[all …]
H A Dpiix4.c63 static void pm_tmr_timer(ACPIREGS *ar) in pm_tmr_timer() argument
65 PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); in pm_tmr_timer()
66 acpi_update_sci(&s->ar, s->irq); in pm_tmr_timer()
298 acpi_pm1_evt_reset(&s->ar); in piix4_pm_reset()
299 acpi_pm1_cnt_reset(&s->ar); in piix4_pm_reset()
300 acpi_pm_tmr_reset(&s->ar); in piix4_pm_reset()
301 acpi_gpe_reset(&s->ar); in piix4_pm_reset()
302 acpi_update_sci(&s->ar, s->irq); in piix4_pm_reset()
316 acpi_pm1_evt_power_down(&s->ar); in piix4_pm_powerdown_req()
488 acpi_gpe_init(&s->ar, GPE_LEN); in piix4_pm_realize()
[all …]
/qemu/include/hw/acpi/
H A Dacpi.h112 typedef void (*acpi_update_sci_fn)(ACPIREGS *ar);
154 void acpi_pm_tmr_update(ACPIREGS *ar, bool enable);
155 void acpi_pm_tmr_calc_overflow_time(ACPIREGS *ar);
158 void acpi_pm_tmr_reset(ACPIREGS *ar);
161 uint16_t acpi_pm1_evt_get_sts(ACPIREGS *ar);
162 void acpi_pm1_evt_power_down(ACPIREGS *ar);
163 void acpi_pm1_evt_reset(ACPIREGS *ar);
171 void acpi_pm1_cnt_update(ACPIREGS *ar,
173 void acpi_pm1_cnt_reset(ACPIREGS *ar);
176 void acpi_gpe_init(ACPIREGS *ar, uint8_t len);
[all …]
H A Dpiix4.h45 ACPIREGS ar; member
/qemu/target/s390x/tcg/
H A Dcc_helper.c139 if ((a1 > 0 && a2 > 0 && ar < 0) || (a1 < 0 && a2 < 0 && ar >= 0)) { in cc_calc_add_64()
142 if (ar < 0) { in cc_calc_add_64()
144 } else if (ar > 0) { in cc_calc_add_64()
154 if ((a1 >= 0 && a2 < 0 && ar < 0) || (a1 < 0 && a2 > 0 && ar > 0)) { in cc_calc_sub_64()
157 if (ar < 0) { in cc_calc_sub_64()
159 } else if (ar > 0) { in cc_calc_sub_64()
199 if ((a1 > 0 && a2 > 0 && ar < 0) || (a1 < 0 && a2 < 0 && ar >= 0)) { in cc_calc_add_32()
202 if (ar < 0) { in cc_calc_add_32()
204 } else if (ar > 0) { in cc_calc_add_32()
214 if ((a1 >= 0 && a2 < 0 && ar < 0) || (a1 < 0 && a2 > 0 && ar > 0)) { in cc_calc_sub_32()
[all …]
H A Dmisc_helper.c765 uint32_t ar) in HELPER()
770 stpcifc_service_call(cpu, r1, fiba, ar, GETPC()); in HELPER()
798 uint64_t gaddr, uint32_t ar) in HELPER()
803 pcistb_service_call(cpu, r1, r3, gaddr, ar, GETPC()); in HELPER()
808 uint32_t ar) in HELPER()
813 mpcifc_service_call(cpu, r1, fiba, ar, GETPC()); in HELPER()
/qemu/target/i386/hvf/
H A Dx86_descr.c80 desc->ar = rvmcs(cpu->accel->fd, vmx_segment_fields[seg].ar_bytes); in vmx_read_segment_descriptor()
90 wvmcs(cpu->accel->fd, sf->ar_bytes, desc->ar); in vmx_write_segment_descriptor()
101 vmx_desc->ar = (selector.sel ? 0 : 1) << 16 | in x86_segment_descriptor_to_vmx()
118 desc->type = vmx_desc->ar & 15; in vmx_segment_to_x86_descriptor()
119 desc->s = (vmx_desc->ar >> 4) & 1; in vmx_segment_to_x86_descriptor()
120 desc->dpl = (vmx_desc->ar >> 5) & 3; in vmx_segment_to_x86_descriptor()
121 desc->p = (vmx_desc->ar >> 7) & 1; in vmx_segment_to_x86_descriptor()
122 desc->avl = (vmx_desc->ar >> 12) & 1; in vmx_segment_to_x86_descriptor()
123 desc->l = (vmx_desc->ar >> 13) & 1; in vmx_segment_to_x86_descriptor()
124 desc->db = (vmx_desc->ar >> 14) & 1; in vmx_segment_to_x86_descriptor()
[all …]
H A Dx86hvf.c45 vmx_seg->ar = 1 << 16; in hvf_set_segment()
48 vmx_seg->ar = (qseg->flags >> DESC_TYPE_SHIFT) & 0xf; in hvf_set_segment()
49 vmx_seg->ar |= ((qseg->flags >> DESC_G_SHIFT) & 1) << 15; in hvf_set_segment()
50 vmx_seg->ar |= ((qseg->flags >> DESC_B_SHIFT) & 1) << 14; in hvf_set_segment()
51 vmx_seg->ar |= ((qseg->flags >> DESC_L_SHIFT) & 1) << 13; in hvf_set_segment()
53 vmx_seg->ar |= ((qseg->flags >> DESC_P_SHIFT) & 1) << 7; in hvf_set_segment()
54 vmx_seg->ar |= ((qseg->flags >> DESC_DPL_SHIFT) & 3) << 5; in hvf_set_segment()
55 vmx_seg->ar |= ((qseg->flags >> DESC_S_SHIFT) & 1) << 4; in hvf_set_segment()
63 qseg->flags = ((vmx_seg->ar & 0xf) << DESC_TYPE_SHIFT) | in hvf_get_segment()
64 (((vmx_seg->ar >> 4) & 1) << DESC_S_SHIFT) | in hvf_get_segment()
[all …]
H A Dx86_descr.h28 uint64_t ar; member
/qemu/tests/unit/
H A Dtest-vmstate.c537 TestStructTriv *ar[AR_SIZE]; member
562 TestArrayOfPtrToStuct sample = {.ar = {&ar[0], &ar[1], &ar[2], &ar[3]} }; in test_arr_ptr_str_no0_save()
571 TestStructTriv ar[AR_SIZE] = {}; in test_arr_ptr_str_no0_load() local
572 TestArrayOfPtrToStuct obj = {.ar = {&ar[0], &ar[1], &ar[2], &ar[3]} }; in test_arr_ptr_str_no0_load()
595 TestArrayOfPtrToStuct sample = {.ar = {&ar[0], NULL, &ar[2], &ar[3]} }; in test_arr_ptr_str_0_save()
604 TestStructTriv ar[AR_SIZE] = {}; in test_arr_ptr_str_0_load() local
605 TestArrayOfPtrToStuct obj = {.ar = {&ar[0], NULL, &ar[2], &ar[3]} }; in test_arr_ptr_str_0_load()
625 int32_t *ar[AR_SIZE]; member
641 int32_t ar[AR_SIZE] = {0 , 1, 2, 3}; in test_arr_ptr_prim_0_save() local
642 TestArrayOfPtrToInt sample = {.ar = {&ar[0], NULL, &ar[2], &ar[3]} }; in test_arr_ptr_prim_0_save()
[all …]
/qemu/tests/tcg/s390x/
H A Dlae.c11 unsigned long long ar = -1, b2 = 100000, r, x2 = 500; in main() local
23 : [tmp] "=&r" (tmp), "=&r" (r2), [ar] "+r" (ar) in main()
27 assert(ar == 0xffffffff00000000ULL); in main()
/qemu/target/s390x/
H A Dioinst.c23 uint8_t *ar) in get_address_from_regs() argument
33 *ar = 0; in get_address_from_regs()
36 return decode_basedisp_s(env, ipb, ar); in get_address_from_regs()
140 uint8_t ar; in ioinst_handle_msch() local
142 addr = get_address_from_regs(env, ipb, &ar); in ioinst_handle_msch()
199 uint8_t ar; in ioinst_handle_ssch() local
201 addr = get_address_from_regs(env, ipb, &ar); in ioinst_handle_ssch()
233 uint8_t ar; in ioinst_handle_stcrw() local
235 addr = get_address_from_regs(env, ipb, &ar); in ioinst_handle_stcrw()
269 uint8_t ar; in ioinst_handle_stsch() local
[all …]
H A Dcpu.h687 void insert_stsi_15_1_x(S390CPU *cpu, int sel2, uint64_t addr, uint8_t ar, uintptr_t ra);
935 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
937 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \ argument
938 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
939 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \ argument
940 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
941 #define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len) \ argument
942 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false)
943 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \ argument
944 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
H A Ds390x-internal.h207 uint8_t *ar) in decode_basedisp_s() argument
217 if (ar) { in decode_basedisp_s()
218 *ar = reg; in decode_basedisp_s()
/qemu/hw/isa/
H A Dvt82c686.c49 ACPIREGS ar; member
90 VMSTATE_UINT16(ar.pm1.evt.sts, ViaPMState),
91 VMSTATE_UINT16(ar.pm1.evt.en, ViaPMState),
148 pmsts = acpi_pm1_evt_get_sts(&s->ar); in pm_update_sci()
149 sci_level = (((pmsts & s->ar.pm1.evt.en) & in pm_update_sci()
167 acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && in pm_update_sci()
171 static void pm_tmr_timer(ACPIREGS *ar) in pm_tmr_timer() argument
173 ViaPMState *s = container_of(ar, ViaPMState, ar); in pm_tmr_timer()
188 acpi_pm1_evt_reset(&s->ar); in via_pm_reset()
189 acpi_pm1_cnt_reset(&s->ar); in via_pm_reset()
[all …]
/qemu/include/hw/s390x/
H A Ds390-pci-inst.h108 uint8_t ar, uintptr_t ra);
109 int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar,
111 int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar,
/qemu/linux-user/m68k/
H A Dcpu_loop.c46 force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, env->mmu.ar); in cpu_loop()
49 force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->mmu.ar); in cpu_loop()
52 force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_TRACE, env->mmu.ar); in cpu_loop()
/qemu/target/s390x/kvm/
H A Dkvm.c798 .ar = ar, in kvm_s390_mem_op()
1261 uint8_t *ar) in get_base_disp_rxy() argument
1272 if (ar) { in get_base_disp_rxy()
1273 *ar = base2; in get_base_disp_rxy()
1281 uint8_t *ar) in get_base_disp_rsy() argument
1291 if (ar) { in get_base_disp_rsy()
1292 *ar = base2; in get_base_disp_rsy()
1337 uint8_t ar; in kvm_stpcifc_service_call() local
1340 fiba = get_base_disp_rxy(cpu, run, &ar); in kvm_stpcifc_service_call()
1384 uint8_t ar; in kvm_pcistb_service_call() local
[all …]
/qemu/hw/timer/
H A Domap_gptimer.c63 int ar; member
164 if (!timer->ar) { in omap_gp_timer_tick()
252 s->ar = 0; in omap_gp_timer_reset()
297 (s->ar << 1) | in omap_gp_timer_readw()
394 s->ar = (value >> 1) & 1; in omap_gp_timer_write()
/qemu/target/i386/
H A Dhelper.c372 static void emit_guest_memory_failure(MemoryFailureAction action, bool ar, in emit_guest_memory_failure()
375 MemoryFailureFlags mff = {.action_required = ar, .recursive = recursive}; in emit_guest_memory_failure()
390 bool ar = !!(params->status & MCI_STATUS_AR); in do_inject_x86_mce()
399 if (!(params->flags & MCE_INJECT_UNCOND_AO) && !ar && recursive) { in do_inject_x86_mce()
400 emit_guest_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, ar, recursive); in do_inject_x86_mce()
439 emit_guest_memory_failure(MEMORY_FAILURE_ACTION_RESET, ar, in do_inject_x86_mce()
467 emit_guest_memory_failure(MEMORY_FAILURE_ACTION_INJECT, ar, recursive); in cpu_x86_inject_mce()
368 emit_guest_memory_failure(MemoryFailureAction action,bool ar,bool recursive) emit_guest_memory_failure() argument
386 bool ar = !!(params->status & MCI_STATUS_AR); do_inject_x86_mce() local
/qemu/scripts/
H A Drender_block_graph.py100 ar = ['virsh', 'qemu-monitor-command', self.name, json.dumps(m)]
102 reply = json.loads(subprocess.check_output(ar))
/qemu/hw/display/
H A Dvga.c347 val = s->ar[index]; in vga_ioport_read()
438 s->ar[index] = val & 0x3f; in vga_ioport_write()
441 s->ar[index] = val & ~0x10; in vga_ioport_write()
444 s->ar[index] = val; in vga_ioport_write()
447 s->ar[index] = val & ~0xc0; in vga_ioport_write()
450 s->ar[index] = val & ~0xf0; in vga_ioport_write()
453 s->ar[index] = val & ~0xf0; in vga_ioport_write()
1045 v = s->ar[i]; in update_palette16()
1046 if (s->ar[VGA_ATC_MODE] & 0x80) { in update_palette16()
1113 params->hpel = s->ar[VGA_ATC_PEL]; in vga_get_params()
[all …]
H A Dvga-helpers.h108 plane_mask = mask16[vga->ar[VGA_ATC_PLANE_ENABLE] & 0xf]; in vga_draw_line2()
150 plane_mask = mask16[vga->ar[VGA_ATC_PLANE_ENABLE] & 0xf]; in vga_draw_line2d2()
189 plane_mask = mask16[vga->ar[VGA_ATC_PLANE_ENABLE] & 0xf]; in vga_draw_line4()
227 plane_mask = mask16[vga->ar[VGA_ATC_PLANE_ENABLE] & 0xf]; in vga_draw_line4d2()
/qemu/target/m68k/
H A Dop_helper.c354 cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0); in m68k_interrupt_all()
357 cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0); in m68k_interrupt_all()
372 cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0); in m68k_interrupt_all()
379 env->mmu.ssw, env->mmu.ar, env->sfc, env->dfc); in m68k_interrupt_all()
395 do_stack_frame(env, &sp, 2, oldsr, env->mmu.ar, env->pc); in m68k_interrupt_all()
491 env->mmu.ar = addr; in m68k_cpu_transaction_failed()
555 env->mmu.ar = env->pc; in raise_exception_format2()
/qemu/tests/docker/dockerfiles/
H A Ddebian-riscv64-cross.docker65 ar = '/usr/bin/riscv64-linux-gnu-gcc-ar'\n\

123