/qemu/contrib/vhost-user-gpu/ |
H A D | virgl.c | 225 struct virtio_gpu_box box; in virgl_cmd_transfer_to_host_2d() local 229 box.x = t2d.r.x; in virgl_cmd_transfer_to_host_2d() 230 box.y = t2d.r.y; in virgl_cmd_transfer_to_host_2d() 231 box.z = 0; in virgl_cmd_transfer_to_host_2d() 232 box.w = t2d.r.width; in virgl_cmd_transfer_to_host_2d() 233 box.h = t2d.r.height; in virgl_cmd_transfer_to_host_2d() 234 box.d = 1; in virgl_cmd_transfer_to_host_2d() 241 (struct virgl_box *)&box, in virgl_cmd_transfer_to_host_2d() 258 (struct virgl_box *)&t3d.box, in virgl_cmd_transfer_to_host_3d() 275 (struct virgl_box *)&tf3d.box, in virgl_cmd_transfer_from_host_3d()
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/qemu/hw/display/ |
H A D | virtio-gpu-virgl.c | 243 struct virtio_gpu_box box; in virgl_cmd_transfer_to_host_2d() local 248 box.x = t2d.r.x; in virgl_cmd_transfer_to_host_2d() 249 box.y = t2d.r.y; in virgl_cmd_transfer_to_host_2d() 250 box.z = 0; in virgl_cmd_transfer_to_host_2d() 251 box.w = t2d.r.width; in virgl_cmd_transfer_to_host_2d() 252 box.h = t2d.r.height; in virgl_cmd_transfer_to_host_2d() 253 box.d = 1; in virgl_cmd_transfer_to_host_2d() 260 (struct virgl_box *)&box, in virgl_cmd_transfer_to_host_2d() 277 (struct virgl_box *)&t3d.box, in virgl_cmd_transfer_to_host_3d() 295 (struct virgl_box *)&tf3d.box, in virgl_cmd_transfer_from_host_3d()
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H A D | virtio-gpu-rutabaga.c | 405 transfer.x = t3d.box.x; in rutabaga_cmd_transfer_to_host_3d() 406 transfer.y = t3d.box.y; in rutabaga_cmd_transfer_to_host_3d() 407 transfer.z = t3d.box.z; in rutabaga_cmd_transfer_to_host_3d() 408 transfer.w = t3d.box.w; in rutabaga_cmd_transfer_to_host_3d() 409 transfer.h = t3d.box.h; in rutabaga_cmd_transfer_to_host_3d() 410 transfer.d = t3d.box.d; in rutabaga_cmd_transfer_to_host_3d() 434 transfer.x = t3d.box.x; in rutabaga_cmd_transfer_from_host_3d() 435 transfer.y = t3d.box.y; in rutabaga_cmd_transfer_from_host_3d() 436 transfer.z = t3d.box.z; in rutabaga_cmd_transfer_from_host_3d() 437 transfer.w = t3d.box.w; in rutabaga_cmd_transfer_from_host_3d() [all …]
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/qemu/ui/ |
H A D | dbus-listener.c | 572 pixman_box32_t *box; in dbus_gl_refresh() local 573 box = pixman_region32_rectangles(&ddl->gl_damage, NULL) + i; in dbus_gl_refresh() 575 dbus_call_update_gl(dcl, box->x1, box->y1, in dbus_gl_refresh() 576 box->x2 - box->x1, box->y2 - box->y1); in dbus_gl_refresh()
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H A D | gtk.c | 1934 GtkWidget *box; in gd_vc_vte_init() local 1975 box = gtk_box_new(GTK_ORIENTATION_HORIZONTAL, 2); in gd_vc_vte_init() 1978 gtk_box_pack_end(GTK_BOX(box), scrollbar, FALSE, FALSE, 0); in gd_vc_vte_init() 1979 gtk_box_pack_end(GTK_BOX(box), vc->vte.terminal, TRUE, TRUE, 0); in gd_vc_vte_init() 1981 vc->vte.box = box; in gd_vc_vte_init() 1988 vc->tab_item = box; in gd_vc_vte_init()
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H A D | cocoa.m | 271 /* Displays an alert dialog box with the specified message */ 1478 /* Displays a dialog box asking the user to select an image file to load.
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/qemu/docs/specs/ |
H A D | pci-serial.rst | 9 guests work out-of-the box with all cards. There is a Windows inf file
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/qemu/docs/system/arm/ |
H A D | realview.rst | 6 certain Linux kernel configurations work out of the box on these boards.
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/qemu/include/ui/ |
H A D | gtk.h | 65 GtkWidget *box; member
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/qemu/include/standard-headers/linux/ |
H A D | virtio_gpu.h | 256 struct virtio_gpu_box box; member
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/qemu/docs/sphinx-static/ |
H A D | theme_overrides.css | 47 box-shadow: 0 4px 8px 0 rgba(0,0,0,0.2), 0 3px 10px 0 rgba(0,0,0,0.19);
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/qemu/docs/system/devices/ |
H A D | virtio-gpu.rst | 50 Mesa's implementations (LLVMpipe, Lavapipe and virgl below) work out of box
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/qemu/docs/system/ppc/ |
H A D | amigang.rst | 149 The only Linux distro that supported Sam460ex out of box was CruxPPC
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/qemu/docs/system/ |
H A D | vnc-security.rst | 23 This ensures that only users on local box with read/write access to that
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/qemu/docs/system/riscv/ |
H A D | sifive_u.rst | 313 board on QEMU ``sifive_u`` machine out of the box. This allows users to
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/qemu/docs/devel/ |
H A D | kconfig.rst | 43 configuration and dependencies can be treated as a black box when building
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/qemu/target/riscv/insn_trans/ |
H A D | trans_rvv.c.inc | 2280 /* NaN-box f[rs1] */ 2626 /* NaN-box f[rs1] */ 2644 /* NaN-box f[rs1] */ 3340 /* NaN-box f[rd] as necessary for SEW */ 3370 /* NaN-box f[rs1] */
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