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/qemu/docs/
H A Dpcie_pci_bridge.txt29 any device plugged in, has no free buses reserved to provide any of them
32 To solve this problem we reserve additional buses on a firmware level.
49 uint32_t bus_res; Minimum number of buses to reserve
H A Dpcie.txt198 Each PCI domain can have up to only 256 buses and the QEMU PCI Express
214 number space. All bus numbers assigned to the buses recursively behind a
222 The PCI Express root buses (pcie.0 and the buses exposed by pxb-pcie devices)
H A Dqdev-device-use.txt6 more buses for children. You can specify a device's parent bus with
9 A device typically has a device address on its parent bus. For buses
33 device. For instance, the IDE controller provides two IDE buses, each
52 TYPE, BUS and UNIT identify the controller device, which of its buses
H A Dpci_expander_bridge.txt8 the main host bridge to support multiple PCI root buses.
/qemu/docs/system/arm/
H A Dpalm.rst17 Audio CODEC, connected through MicroWire and |I2S| buses
H A Dxscale.rst35 - WM8750 audio CODEC on |I2C| and |I2S| buses
H A Dxlnx-versal-virt.rst241 To connect CANFD0 and CANFD1 to separate buses:
/qemu/hw/pci/
H A Dmeson.build15 # allow plugging PCIe devices into PCI buses, include them even if
/qemu/docs/system/
H A Ddevice-emulation.rst33 machine model you choose (``-M foo``) a number of buses will have been
42 additional buses to the system that other devices can be attached to.
/qemu/docs/system/devices/
H A Dcan.rst4 emulated CAN controller chips together by one or multiple CAN buses
5 (the controller device "canbus" parameter). The individual buses
9 The concept of buses is generic and different CAN controllers
H A Dusb.rst40 bus though, so there are two completely separate USB buses: One USB
353 same physical port on the host may show up on different host buses
/qemu/docs/specs/
H A Dfsi.rst13 FSI allows a service processor access to the internal buses of a host POWER
22 "engines" that drive accesses on buses internal and external to the POWER
/qemu/docs/devel/
H A Dkconfig.rst16 Each QEMU target enables a subset of the boards, devices and buses that
141 **subsystems**, of which **buses** are a special case
153 subsystems or buses. For example, ``AUX`` (the DisplayPort auxiliary
172 have no ``depends on`` directive. Devices also *select* the buses
H A Dqtest.rst29 communicating with system buses or devices. Many virtual device tests use
H A Dreset.rst241 for devices and buses and should be preferred.
333 child buses, and all the devices on those child buses.
H A Dmemory.rst5 The memory API models the memory and I/O buses and controllers of a QEMU
21 buses, memory controllers, and memory regions that have been rerouted.
H A Dmulti-process.rst728 argument. For buses that assign addresses to devices dynamically, this
/qemu/hw/ssi/
H A Dxilinx_spips.c256 uint8_t buses; in xlnx_zynqmp_qspips_update_cs_lines() local
259 buses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT); in xlnx_zynqmp_qspips_update_cs_lines()
260 bus0_enabled = buses & 1; in xlnx_zynqmp_qspips_update_cs_lines()
261 bus1_enabled = buses & (1 << 1); in xlnx_zynqmp_qspips_update_cs_lines()