Searched refs:buses (Results 1 – 18 of 18) sorted by relevance
/qemu/docs/ |
H A D | pcie_pci_bridge.txt | 29 any device plugged in, has no free buses reserved to provide any of them 32 To solve this problem we reserve additional buses on a firmware level. 49 uint32_t bus_res; Minimum number of buses to reserve
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H A D | pcie.txt | 198 Each PCI domain can have up to only 256 buses and the QEMU PCI Express 214 number space. All bus numbers assigned to the buses recursively behind a 222 The PCI Express root buses (pcie.0 and the buses exposed by pxb-pcie devices)
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H A D | qdev-device-use.txt | 6 more buses for children. You can specify a device's parent bus with 9 A device typically has a device address on its parent bus. For buses 33 device. For instance, the IDE controller provides two IDE buses, each 52 TYPE, BUS and UNIT identify the controller device, which of its buses
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H A D | pci_expander_bridge.txt | 8 the main host bridge to support multiple PCI root buses.
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/qemu/docs/system/arm/ |
H A D | palm.rst | 17 Audio CODEC, connected through MicroWire and |I2S| buses
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H A D | xscale.rst | 35 - WM8750 audio CODEC on |I2C| and |I2S| buses
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H A D | xlnx-versal-virt.rst | 241 To connect CANFD0 and CANFD1 to separate buses:
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/qemu/hw/pci/ |
H A D | meson.build | 15 # allow plugging PCIe devices into PCI buses, include them even if
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/qemu/docs/system/ |
H A D | device-emulation.rst | 33 machine model you choose (``-M foo``) a number of buses will have been 42 additional buses to the system that other devices can be attached to.
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/qemu/docs/system/devices/ |
H A D | can.rst | 4 emulated CAN controller chips together by one or multiple CAN buses 5 (the controller device "canbus" parameter). The individual buses 9 The concept of buses is generic and different CAN controllers
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H A D | usb.rst | 40 bus though, so there are two completely separate USB buses: One USB 353 same physical port on the host may show up on different host buses
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/qemu/docs/specs/ |
H A D | fsi.rst | 13 FSI allows a service processor access to the internal buses of a host POWER 22 "engines" that drive accesses on buses internal and external to the POWER
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/qemu/docs/devel/ |
H A D | kconfig.rst | 16 Each QEMU target enables a subset of the boards, devices and buses that 141 **subsystems**, of which **buses** are a special case 153 subsystems or buses. For example, ``AUX`` (the DisplayPort auxiliary 172 have no ``depends on`` directive. Devices also *select* the buses
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H A D | qtest.rst | 29 communicating with system buses or devices. Many virtual device tests use
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H A D | reset.rst | 241 for devices and buses and should be preferred. 333 child buses, and all the devices on those child buses.
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H A D | memory.rst | 5 The memory API models the memory and I/O buses and controllers of a QEMU 21 buses, memory controllers, and memory regions that have been rerouted.
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H A D | multi-process.rst | 728 argument. For buses that assign addresses to devices dynamically, this
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/qemu/hw/ssi/ |
H A D | xilinx_spips.c | 256 uint8_t buses; in xlnx_zynqmp_qspips_update_cs_lines() local 259 buses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT); in xlnx_zynqmp_qspips_update_cs_lines() 260 bus0_enabled = buses & 1; in xlnx_zynqmp_qspips_update_cs_lines() 261 bus1_enabled = buses & (1 << 1); in xlnx_zynqmp_qspips_update_cs_lines()
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