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Searched refs:cause (Results 1 – 25 of 75) sorted by relevance

123

/qemu/target/ppc/
H A Dmisc_helper.c91 const char *caller, uint32_t cause, in raise_hv_fu_exception() argument
99 raise_exception_err_ra(env, POWERPC_EXCP_HV_FU, cause, raddr); in raise_hv_fu_exception()
103 uint32_t sprn, uint32_t cause, in raise_fu_exception() argument
109 cause &= FSCR_IC_MASK; in raise_fu_exception()
110 env->spr[SPR_FSCR] |= (target_ulong)cause << FSCR_IC_POS; in raise_fu_exception()
117 const char *caller, uint32_t cause) in helper_hfscr_facility_check() argument
122 raise_hv_fu_exception(env, bit, caller, cause, GETPC()); in helper_hfscr_facility_check()
128 uint32_t sprn, uint32_t cause) in helper_fscr_facility_check() argument
135 raise_fu_exception(env, bit, sprn, cause, GETPC()); in helper_fscr_facility_check()
140 uint32_t sprn, uint32_t cause) in helper_msr_facility_check() argument
[all …]
H A Dmmu-radix64.c113 vaddr eaddr, uint32_t cause) in ppc_radix64_raise_si() argument
120 eaddr, cause); in ppc_radix64_raise_si()
126 env->error_code = cause; in ppc_radix64_raise_si()
129 cause |= DSISR_ISSTORE; in ppc_radix64_raise_si()
134 env->spr[SPR_DSISR] = cause; in ppc_radix64_raise_si()
144 vaddr eaddr, hwaddr g_raddr, uint32_t cause) in ppc_radix64_raise_hsi() argument
150 if (cause & DSISR_PRTABLE_FAULT) { in ppc_radix64_raise_hsi()
159 eaddr, g_raddr, cause); in ppc_radix64_raise_hsi()
166 env->error_code = cause; in ppc_radix64_raise_hsi()
169 cause |= DSISR_ISSTORE; in ppc_radix64_raise_hsi()
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/qemu/target/mips/tcg/sysemu/
H A Dtlb_helper.c1034 int cause = -1; in mips_cpu_do_interrupt() local
1130 cause = 0; in mips_cpu_do_interrupt()
1162 cause = 1; in mips_cpu_do_interrupt()
1166 cause = 2; in mips_cpu_do_interrupt()
1187 cause = 3; in mips_cpu_do_interrupt()
1208 cause = 4; in mips_cpu_do_interrupt()
1212 cause = 5; in mips_cpu_do_interrupt()
1216 cause = 6; in mips_cpu_do_interrupt()
1219 cause = 7; in mips_cpu_do_interrupt()
1222 cause = 8; in mips_cpu_do_interrupt()
[all …]
/qemu/target/xtensa/
H A Dexc_helper.c48 void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t cause) in HELPER()
65 env->sregs[EXCCAUSE] = cause; in HELPER()
72 uint32_t pc, uint32_t cause, uint32_t vaddr) in HELPER()
75 HELPER(exception_cause)(env, pc, cause); in HELPER()
78 void debug_exception_env(CPUXtensaState *env, uint32_t cause) in debug_exception_env() argument
81 HELPER(debug_exception)(env, env->pc, cause); in debug_exception_env()
85 void HELPER(debug_exception)(CPUXtensaState *env, uint32_t pc, uint32_t cause) in HELPER()
90 env->sregs[DEBUGCAUSE] = cause; in HELPER()
H A Dhelper.c224 uint32_t cause; in xtensa_breakpoint_handler() local
227 cause = check_hw_breakpoints(env); in xtensa_breakpoint_handler()
228 if (cause) { in xtensa_breakpoint_handler()
229 debug_exception_env(env, cause); in xtensa_breakpoint_handler()
/qemu/target/riscv/
H A Dcpu_helper.c1663 !(env->mip & (1 << cause)); in riscv_cpu_do_interrupt()
1665 !(env->mip & (1 << cause)); in riscv_cpu_do_interrupt()
1673 switch (cause) { in riscv_cpu_do_interrupt()
1730 if (cause == RISCV_EXCP_U_ECALL) { in riscv_cpu_do_interrupt()
1734 cause = RISCV_EXCP_M_ECALL; in riscv_cpu_do_interrupt()
1736 cause = RISCV_EXCP_VS_ECALL; in riscv_cpu_do_interrupt()
1738 cause = RISCV_EXCP_S_ECALL; in riscv_cpu_do_interrupt()
1740 cause = RISCV_EXCP_U_ECALL; in riscv_cpu_do_interrupt()
1754 if (env->priv <= PRV_S && cause < 64 && in riscv_cpu_do_interrupt()
1767 if (async && (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || in riscv_cpu_do_interrupt()
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H A Dtrace-events2 …4_t hartid, bool async, uint64_t cause, uint64_t epc, uint64_t tval, const char *desc) "hart:%"PRI…
/qemu/target/alpha/
H A Dhelper.c129 target_ulong mmcsr, cause; in alpha_cpu_record_sigsegv() local
135 cause = 0; in alpha_cpu_record_sigsegv()
139 cause = 1; in alpha_cpu_record_sigsegv()
143 cause = -1; in alpha_cpu_record_sigsegv()
161 env->trap_arg2 = cause; in alpha_cpu_record_sigsegv()
/qemu/replay/
H A Dreplay.c73 static const char *replay_shutdown_event_name(ShutdownCause cause) in replay_shutdown_event_name() argument
75 switch (cause) { in replay_shutdown_event_name()
264 void replay_shutdown_request(ShutdownCause cause) in replay_shutdown_request() argument
268 replay_put_event(EVENT_SHUTDOWN + cause); in replay_shutdown_request()
H A Dstubs-system.c44 void replay_shutdown_request(ShutdownCause cause) in replay_shutdown_request() argument
/qemu/include/sysemu/
H A Drunstate.h38 static inline bool shutdown_caused_by_guest(ShutdownCause cause) in shutdown_caused_by_guest() argument
40 return cause >= SHUTDOWN_CAUSE_GUEST_SHUTDOWN; in shutdown_caused_by_guest()
H A Dreplay.h107 void replay_shutdown_request(ShutdownCause cause);
/qemu/target/loongarch/
H A Dcpu.c168 int cause = -1; in loongarch_cpu_do_interrupt() local
199 cause = cs->exception_index; in loongarch_cpu_do_interrupt()
220 cause = cs->exception_index; in loongarch_cpu_do_interrupt()
246 EXCODE_MCODE(cause)); in loongarch_cpu_do_interrupt()
248 EXCODE_SUBCODE(cause)); in loongarch_cpu_do_interrupt()
279 cause, env->CSR_BADV, env->CSR_DERA, vector, in loongarch_cpu_do_interrupt()
285 set_pc(env, env->CSR_EENTRY + EXCODE_MCODE(cause) * vec_size); in loongarch_cpu_do_interrupt()
294 cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT, in loongarch_cpu_do_interrupt()
/qemu/system/
H A Drunstate.c703 static void qemu_system_shutdown(ShutdownCause cause) in qemu_system_shutdown() argument
705 qapi_event_send_shutdown(shutdown_caused_by_guest(cause), cause); in qemu_system_shutdown()
706 notifier_list_notify(&shutdown_notifiers, &cause); in qemu_system_shutdown()
/qemu/target/riscv/insn_trans/
H A Dtrans_rvi.c.inc913 * If rd == 0, the insn shall not read the csr, nor cause any of the
928 * If rd == 0, the insn shall not read the csr, nor cause any of the
944 * cause any of the side effects that might occur on a csr write.
947 * unmodified value back to the csr and will cause side effects.
973 * cause any of the side effects that might occur on a csr write.
976 * unmodified value back to the csr and will cause side effects.
1004 * If rd == 0, the insn shall not read the csr, nor cause any of the
1034 * cause any of the side effects that might occur on a csr write.
1037 * unmodified value back to the csr and will cause side effects.
1062 * cause any of the side effects that might occur on a csr write.
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/qemu/tests/tcg/cris/bare/
H A Dcheck_clrjmp1.s25 ; The corresponding bug would cause this insn too, to set p0.
/qemu/target/rx/
H A Dop_helper.c75 int xcpt, cause, enable; in update_fpsw() local
114 cause = FIELD_EX32(env->fpsw, FPSW, CAUSE); in update_fpsw()
117 if (cause & enable) { in update_fpsw()
/qemu/target/sh4/
H A Dop_helper.c218 int xcpt, cause, enable; in update_fpscr() local
247 cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT; in update_fpscr()
249 if (cause & enable) { in update_fpscr()
/qemu/docs/devel/
H A Dtcg-icount.rst41 translated block and will cause a return to the outer loop to deal
46 would cause the instruction budget to go negative we exit the main
H A Dsecure-coding-practices.rst84 request completes. Unexpected accesses must not cause memory corruption or
104 time-of-check-to-time-of-use (TOCTOU) race conditions that could cause QEMU to
/qemu/hw/net/
H A De1000e_core.c908 uint32_t cause = E1000_ICS_TXQE; in e1000e_start_xmit() local
929 if (!ide || !e1000e_intrmgr_delay_tx_causes(core, &cause)) { in e1000e_start_xmit()
930 e1000e_set_interrupt_cause(core, cause); in e1000e_start_xmit()
1992 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); in e1000e_msix_notify_one()
1995 trace_e1000e_wrn_msix_invalid(cause, int_cfg); in e1000e_msix_notify_one()
1999 trace_e1000e_irq_iam_clear_eiame(core->mac[IAM], cause); in e1000e_msix_notify_one()
2000 core->mac[IAM] &= ~cause; in e1000e_msix_notify_one()
2005 effective_eiac = core->mac[EIAC] & cause; in e1000e_msix_notify_one()
2049 trace_e1000e_irq_msix_pending_clearing(cause, int_cfg, vec); in e1000e_msix_clear_one()
2052 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); in e1000e_msix_clear_one()
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/qemu/.gitlab-ci.d/
H A Dcustom-runners.yml10 # gitlab-runner. To avoid problems that gitlab-runner can cause while
/qemu/docs/system/
H A Dgeneric-loader.rst90 optional argument and will cause the CPU's PC to be set to the
93 be used for the boot image. This will also cause the image to be
/qemu/docs/devel/migration/
H A Dbest-practices.rst34 - Changes in firmware size can cause changes in the required RAMBlock size
/qemu/python/qemu/qmp/
H A Dprotocol.py90 cause = str(self.exc)
91 if not cause:
93 cause = exception_summary(self.exc)

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