/qemu/hw/dma/ |
H A D | etraxfs_dma.c | 326 if (!channel_en(ctrl, c) in channel_continue() 341 channel_load_d(ctrl, c); in channel_continue() 345 if (!ctrl->channels[c].current_d.eol && ctrl->channels[c].eol) { in channel_continue() 404 if (ctrl->channels[c].eol) in channel_out_run() 505 channel_load_d(ctrl, c); in channel_in_process() 747 cl->ctrl = ctrl; in etraxfs_dmac_connect_client() 769 ctrl = g_malloc0(sizeof *ctrl); in etraxfs_dmac_init() 771 ctrl->bh = qemu_bh_new(DMA_run, ctrl); in etraxfs_dmac_init() 774 ctrl->channels = g_malloc0(sizeof ctrl->channels[0] * nr_channels); in etraxfs_dmac_init() 776 memory_region_init_io(&ctrl->mmio, NULL, &dma_ops, ctrl, "etraxfs-dma", in etraxfs_dmac_init() [all …]
|
H A D | pl080.c | 46 VMSTATE_UINT32(ctrl, pl080_channel), 139 size = ch->ctrl & 0xfff; in pl080_run() 165 swidth = 1 << ((ch->ctrl >> 18) & 7); in pl080_run() 166 dwidth = 1 << ((ch->ctrl >> 21) & 7); in pl080_run() 170 if (ch->ctrl & PL080_CCTRL_SI) in pl080_run() 178 if (ch->ctrl & PL080_CCTRL_DI) in pl080_run() 183 ch->ctrl = (ch->ctrl & 0xfffff000) | size; in pl080_run() 206 if (ch->ctrl & PL080_CCTRL_I) { in pl080_run() 243 return s->chan[i].ctrl; in pl080_read() 307 s->chan[i].ctrl = value; in pl080_write() [all …]
|
/qemu/target/riscv/ |
H A D | debug.c | 253 sizelo = extract32(ctrl, 16, 2); in type2_breakpoint_size() 314 if (ctrl & TYPE2_EXEC) { in type2_breakpoint_insert() 318 if (ctrl & TYPE2_LOAD) { in type2_breakpoint_insert() 321 if (ctrl & TYPE2_STORE) { in type2_breakpoint_insert() 412 size = extract32(ctrl, 16, 4); in type6_mcontrol6_validate() 417 val |= (ctrl & TYPE6_SIZE); in type6_mcontrol6_validate() 440 if (ctrl & TYPE6_EXEC) { in type6_breakpoint_insert() 444 if (ctrl & TYPE6_LOAD) { in type6_breakpoint_insert() 448 if (ctrl & TYPE6_STORE) { in type6_breakpoint_insert() 779 target_ulong ctrl; in riscv_cpu_debug_check_breakpoint() local [all …]
|
/qemu/hw/usb/ |
H A D | hcd-uhci.c | 327 port->ctrl = 0x0080; in uhci_reset() 521 val = port->ctrl; in uhci_port_read() 601 if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) { in uhci_wakeup() 629 le32_to_cpus(&td->ctrl); in uhci_read_td() 642 td->ctrl |= TD_CTRL_NAK; in uhci_handle_td_error() 668 td->ctrl &= ~TD_CTRL_ACTIVE; in uhci_handle_td_error() 670 if (td->ctrl & TD_CTRL_IOC) { in uhci_handle_td_error() 685 if (td->ctrl & TD_CTRL_IOS) in uhci_complete_td() 694 td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); in uhci_complete_td() 700 if (td->ctrl & TD_CTRL_IOC) in uhci_complete_td() [all …]
|
H A D | hcd-ohci.c | 330 port->ctrl = 0; in ohci_roothub_reset() 1451 if (ohci->rhport[i].ctrl & val) { in ohci_port_set_if_connected() 1455 ohci->rhport[i].ctrl |= val; in ohci_port_set_if_connected() 1467 old_state = port->ctrl; in ohci_port_set_status() 1474 port->ctrl &= ~OHCI_PORT_PES; in ohci_port_set_status() 1497 if (old_state != port->ctrl) { in ohci_port_set_status() 1775 uint32_t old_state = port->ctrl; in ohci_attach() 1794 if (old_state != port->ctrl) { in ohci_attach() 1815 uint32_t old_state = port->ctrl; in ohci_detach() 1822 port->ctrl |= OHCI_PORT_CSC; in ohci_detach() [all …]
|
/qemu/hw/block/ |
H A D | swim.c | 252 drive->swimctrl = bus->ctrl; in swim_drive_realize() 474 SWIMCtrl *ctrl = &sys->ctrl; in sysbus_swim_reset() local 477 ctrl->mode = 0; in sysbus_swim_reset() 478 ctrl->iwm_switch = 0; in sysbus_swim_reset() 479 memset(ctrl->iwmregs, 0, sizeof(ctrl->iwmregs)); in sysbus_swim_reset() 481 ctrl->swim_phase = 0; in sysbus_swim_reset() 482 ctrl->swim_mode = 0; in sysbus_swim_reset() 483 memset(ctrl->ismregs, 0, sizeof(ctrl->ismregs)); in sysbus_swim_reset() 493 SWIMCtrl *swimctrl = &sbs->ctrl; in sysbus_swim_init() 506 SWIMCtrl *swimctrl = &sys->ctrl; in sysbus_swim_realize() [all …]
|
/qemu/pc-bios/s390-ccw/ |
H A D | cio.c | 188 if (irb->scsw.ctrl & SCSW_FCTL_START_FUNC) { in print_irb_err() 191 if (irb->scsw.ctrl & SCSW_FCTL_HALT_FUNC) { in print_irb_err() 194 if (irb->scsw.ctrl & SCSW_FCTL_CLEAR_FUNC) { in print_irb_err() 205 if (irb->scsw.ctrl & SCSW_ACTL_START_PEND) { in print_irb_err() 208 if (irb->scsw.ctrl & SCSW_ACTL_HALT_PEND) { in print_irb_err() 214 if (irb->scsw.ctrl & SCSW_ACTL_CH_ACTIVE) { in print_irb_err() 220 if (irb->scsw.ctrl & SCSW_ACTL_SUSPENDED) { in print_irb_err() 228 if (irb->scsw.ctrl & SCSW_SCTL_ALERT) { in print_irb_err() 231 if (irb->scsw.ctrl & SCSW_SCTL_INTERMED) { in print_irb_err() 234 if (irb->scsw.ctrl & SCSW_SCTL_PRIMARY) { in print_irb_err() [all …]
|
/qemu/hw/s390x/ |
H A D | css.c | 84 VMSTATE_UINT16(ctrl, SCSW), 641 sch->curr_status.scsw.ctrl |= in css_conditional_io_interrupt() 1344 dest->ctrl = cpu_to_be16(src->ctrl); in copy_scsw_to_guest() 1420 dest->ctrl = be16_to_cpu(src->ctrl); in copy_scsw_from_guest() 1463 if (schib->scsw.ctrl & in css_do_msch() 1509 (!(schib->scsw.ctrl & in css_do_xsch() 1541 old_scsw_ctrl = schib->scsw.ctrl; in css_do_csch() 1550 schib->scsw.ctrl = old_scsw_ctrl; in css_do_csch() 1581 old_scsw_ctrl = schib->scsw.ctrl; in css_do_hsch() 1597 schib->scsw.ctrl = old_scsw_ctrl; in css_do_hsch() [all …]
|
/qemu/hw/misc/ |
H A D | mos6522.c | 69 int ctrl; in mos6522_set_irq() local 88 if ((positive_edge && (ctrl & C2_POS)) || in mos6522_set_irq() 95 if ((positive_edge && (ctrl & C1_POS)) || in mos6522_set_irq() 105 if ((positive_edge && (ctrl & C2_POS)) || in mos6522_set_irq() 112 if ((positive_edge && (ctrl & C1_POS)) || in mos6522_set_irq() 300 int ctrl; in mos6522_read() local 315 if (!(ctrl & C2_IND)) { in mos6522_read() 327 if (!(ctrl & C2_IND)) { in mos6522_read() 398 int ctrl; in mos6522_write() local 407 if (!(ctrl & C2_IND)) { in mos6522_write() [all …]
|
H A D | arm_l2x0.c | 40 uint32_t ctrl; member 53 VMSTATE_UINT32(ctrl, L2x0State), 82 return s->ctrl; in l2x0_priv_read() 118 s->ctrl = value & 1; in l2x0_priv_write() 152 s->ctrl = 0; in l2x0_priv_reset()
|
H A D | bcm2835_mphi.c | 52 val = s->ctrl; in mphi_reg_read() 88 s->ctrl = val; in mphi_reg_write() 133 s->ctrl = 0; in mphi_reset() 162 VMSTATE_UINT32(ctrl, BCM2835MphiState),
|
H A D | tz-mpc.c | 133 if (access_size == 4 && (s->ctrl & R_CTRL_AUTOINC_MASK)) { in tz_mpc_autoinc_idx() 158 r = s->ctrl; in tz_mpc_reg_read() 257 oldval = s->ctrl; in tz_mpc_reg_write() 272 if ((s->ctrl & R_CTRL_LOCKDOWN_MASK) && in tz_mpc_reg_write() 287 s->ctrl = value & (R_CTRL_SEC_RESP_MASK | in tz_mpc_reg_write() 385 return (s->ctrl & R_CTRL_SEC_RESP_MASK) ? MEMTX_ERROR : MEMTX_OK; in tz_mpc_handle_block() 476 s->ctrl = 0x00000100; in tz_mpc_reset() 578 VMSTATE_UINT32(ctrl, TZMPC),
|
/qemu/hw/char/ |
H A D | cmsdk-apb-uart.c | 106 s->intstatus |= (s->state & (s->ctrl >> 2) & omask); in cmsdk_apb_uart_update() 120 if (s->ctrl & R_CTRL_RX_EN_MASK && !(s->state & R_STATE_RXFULL_MASK)) { in uart_can_receive() 137 if (!(s->ctrl & R_CTRL_RX_EN_MASK)) { in uart_receive() 148 if (s->ctrl & R_CTRL_RX_INTEN_MASK) { in uart_receive() 170 r = s->ctrl; in uart_read() 201 if (!(s->ctrl & R_CTRL_TX_EN_MASK) || !(s->state & R_STATE_TXFULL_MASK)) { in uart_transmit() 226 if (s->ctrl & R_CTRL_TX_INTEN_MASK) { in uart_transmit() 269 s->ctrl = value & 0x7f; in uart_write() 270 if ((s->ctrl & R_CTRL_TX_EN_MASK) && !uart_baudrate_ok(s)) { in uart_write() 314 s->ctrl = 0; in cmsdk_apb_uart_reset() [all …]
|
/qemu/hw/timer/ |
H A D | cmsdk-apb-timer.c | 83 r = s->ctrl; in cmsdk_apb_timer_read() 123 s->ctrl = value & 0xf; in cmsdk_apb_timer_write() 125 if (s->ctrl & R_CTRL_EN_MASK) { in cmsdk_apb_timer_write() 139 if (value && (s->ctrl & R_CTRL_EN_MASK)) { in cmsdk_apb_timer_write() 154 if (value && (s->ctrl & R_CTRL_EN_MASK)) { in cmsdk_apb_timer_write() 187 if (s->ctrl & R_CTRL_IRQEN_MASK) { in cmsdk_apb_timer_tick() 198 s->ctrl = 0; in cmsdk_apb_timer_reset() 256 VMSTATE_UINT32(ctrl, CMSDKAPBTimer),
|
H A D | etraxfs_timer.c | 152 uint32_t ctrl; in update_ctrl() local 157 ctrl = t->rw_tmr0_ctrl; in update_ctrl() 161 ctrl = t->rw_tmr1_ctrl; in update_ctrl() 167 op = ctrl & 3; in update_ctrl() 168 freq = ctrl >> 2; in update_ctrl()
|
/qemu/target/microblaze/ |
H A D | op_helper.c | 32 int test = ctrl & STREAM_TEST; in helper_put() 33 int atomic = ctrl & STREAM_ATOMIC; in helper_put() 34 int control = ctrl & STREAM_CONTROL; in helper_put() 35 int nonblock = ctrl & STREAM_NONBLOCK; in helper_put() 36 int exception = ctrl & STREAM_EXCEPTION; in helper_put() 47 uint32_t helper_get(uint32_t id, uint32_t ctrl) in helper_get() argument 49 int test = ctrl & STREAM_TEST; in helper_get() 50 int atomic = ctrl & STREAM_ATOMIC; in helper_get() 51 int control = ctrl & STREAM_CONTROL; in helper_get() 52 int nonblock = ctrl & STREAM_NONBLOCK; in helper_get() [all …]
|
/qemu/hw/rtc/ |
H A D | twl92230.c | 61 uint8_t ctrl; member 103 if ((s->rtc.ctrl & 3) == 3) in menelaus_alm_update() 115 if ((s->rtc.ctrl >> 3) & 3) { /* EVERY */ in menelaus_rtc_hz() 177 if (s->rtc.ctrl & 1) in menelaus_reset() 179 s->rtc.ctrl = 0x00; in menelaus_reset() 326 return s->rtc.ctrl; in menelaus_read() 544 if ((s->rtc.ctrl ^ value) & 1) { /* RTC_EN */ in menelaus_write() 550 s->rtc.ctrl = value & 0x1f; in menelaus_write() 795 if (s->rtc.ctrl & 1) /* RTC_EN */ in menelaus_post_load() 802 if (s->rtc.ctrl & 1) /* RTC_EN */ in menelaus_post_load() [all …]
|
/qemu/tests/qtest/ |
H A D | aspeed_smc-test.c | 108 uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0); in spi_ctrl_setmode() local 109 ctrl &= ~(CTRL_USERMODE | 0xff << 16); in spi_ctrl_setmode() 110 ctrl |= mode | (cmd << 16); in spi_ctrl_setmode() 111 writel(ASPEED_FMC_BASE + R_CTRL0, ctrl); in spi_ctrl_setmode() 116 uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0); in spi_ctrl_start_user() local 118 ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE; in spi_ctrl_start_user() 119 writel(ASPEED_FMC_BASE + R_CTRL0, ctrl); in spi_ctrl_start_user() 121 ctrl &= ~CTRL_CE_STOP_ACTIVE; in spi_ctrl_start_user() 122 writel(ASPEED_FMC_BASE + R_CTRL0, ctrl); in spi_ctrl_start_user() 129 ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE; in spi_ctrl_stop_user() [all …]
|
/qemu/hw/vfio/ |
H A D | ccw.c | 332 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; in vfio_ccw_io_notifier_handler() 333 schib->scsw.ctrl |= (SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND); in vfio_ccw_io_notifier_handler() 337 schib->scsw.ctrl &= ~SCSW_ACTL_START_PEND; in vfio_ccw_io_notifier_handler() 339 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; in vfio_ccw_io_notifier_handler() 340 schib->scsw.ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | in vfio_ccw_io_notifier_handler() 345 schib->scsw.ctrl &= ~SCSW_ACTL_START_PEND; in vfio_ccw_io_notifier_handler() 347 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; in vfio_ccw_io_notifier_handler() 348 schib->scsw.ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | in vfio_ccw_io_notifier_handler() 354 schib->scsw.ctrl &= ~SCSW_ACTL_START_PEND; in vfio_ccw_io_notifier_handler() 356 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; in vfio_ccw_io_notifier_handler() [all …]
|
/qemu/hw/ide/ |
H A D | microdrive.c | 61 uint8_t ctrl; member 103 !(s->ctrl & (CTRL_IEN | CTRL_SRST)) && in md_interrupt_update() 128 s->ctrl = 0; in md_reset() 151 if (s->ctrl & CTRL_IEN) { in md_attr_read() 320 s->ctrl = value; in md_common_write() 343 VMSTATE_UINT8(ctrl, MicroDriveState),
|
/qemu/target/i386/ |
H A D | ops_sse.h | 1909 if (ctrl >> 8) { in pcmp_elen() 1914 if (ctrl & 1) { in pcmp_elen() 1929 if (ctrl & 1) { in pcmp_ilen() 1944 switch ((ctrl >> 0) & 3) { in pcmp_val() 1970 switch ((ctrl >> 2) & 3) { in pcmpxstrx() 2008 v &= (pcmp_val(s, ctrl, i + j) == pcmp_val(d, ctrl, i)); in pcmpxstrx() 2015 switch ((ctrl >> 4) & 3) { in pcmpxstrx() 2056 if ((ctrl >> 6) & 1) { in glue() 2057 if (ctrl & 1) { in glue() 2094 if ((ctrl >> 6) & 1) { in glue() [all …]
|
/qemu/ui/ |
H A D | sdl2-input.c | 48 bool ctrl = qkbd_state_modifier_get(scon->kbd, QKBD_MOD_CTRL); in sdl2_process_key() local 55 qemu_text_console_put_qcode(s, qcode, ctrl); in sdl2_process_key()
|
/qemu/hw/ipack/ |
H A D | tpci200.c | 68 uint8_t ctrl[N_MODULES]; member 120 if (!(dev->ctrl[ip_n] & CTRL_INT(intno))) { in tpci200_set_irq() 139 if (dev->ctrl[ip_n] & CTRL_INT_EDGE(intno)) { in tpci200_set_irq() 153 if (dev->ctrl[i] & CTRL_INT_EDGE(j)) { in tpci200_set_irq() 217 ret = s->ctrl[ip_n]; in tpci200_read_las0() 259 s->ctrl[ip_n] = val; in tpci200_write_las0() 345 bool int_edge_sensitive = s->ctrl[ip_n] & CTRL_INT_EDGE(intno); in tpci200_read_las1() 625 VMSTATE_UINT8_ARRAY(ctrl, TPCI200State, N_MODULES),
|
/qemu/include/hw/timer/ |
H A D | npcm7xx_timer.h | 61 NPCM7xxTimerCtrlState *ctrl; member 79 NPCM7xxTimerCtrlState *ctrl; member
|
/qemu/include/hw/block/ |
H A D | swim.h | 36 struct SWIMCtrl *ctrl; member 70 SWIMCtrl ctrl; member
|