Searched refs:ctz32 (Results 1 – 25 of 95) sorted by relevance
1234
32 #define PCI_EXP_FLAGS_IRQ_SHIFT ctz32(PCI_EXP_FLAGS_IRQ)33 #define PCI_EXP_FLAGS_TYPE_SHIFT ctz32(PCI_EXP_FLAGS_TYPE)59 #define PCI_EXP_LNK_MLW_SHIFT ctz32(PCI_EXP_LNKCAP_MLW)64 #define PCI_EXP_LNKCAP_ASPMS_SHIFT ctz32(PCI_EXP_LNKCAP_ASPMS)67 #define PCI_EXP_LNKCAP_PN_SHIFT ctz32(PCI_EXP_LNKCAP_PN)69 #define PCI_EXP_SLTCAP_PSN_SHIFT ctz32(PCI_EXP_SLTCAP_PSN)120 #define PCI_ERR_ROOT_IRQ_SHIFT ctz32(PCI_ERR_ROOT_IRQ)
574 rval = reg << ctz32(mask); in pci_set_byte_by_mask()585 rval = reg << ctz32(mask); in pci_set_word_by_mask()596 rval = reg << ctz32(mask); in pci_set_long_by_mask()607 rval = reg << ctz32(mask); in pci_set_quad_by_mask()
90 ((flags & PCI_MSI_FLAGS_QSIZE) >> ctz32(PCI_MSI_FLAGS_QSIZE)); in msi_nr_vectors()216 vectors_order = ctz32(nr_vectors); in msi_init()218 flags = vectors_order << ctz32(PCI_MSI_FLAGS_QMASK); in msi_init()452 (flags & PCI_MSI_FLAGS_QSIZE) >> ctz32(PCI_MSI_FLAGS_QSIZE); in msi_write_config()454 (flags & PCI_MSI_FLAGS_QMASK) >> ctz32(PCI_MSI_FLAGS_QMASK); in msi_write_config()457 flags |= log_max_vecs << ctz32(PCI_MSI_FLAGS_QSIZE); in msi_write_config()
8 #define SLOTID_NSLOTS_SHIFT ctz32(PCI_SID_ESR_NSLOTS)
65 ctz32(SHPC_SLOT_STATE_MASK)74 ctz32(SHPC_SLOT_PWR_LED_MASK)77 ctz32(SHPC_SLOT_ATTN_LED_MASK)158 uint16_t result = (pci_get_word(status) & msk) >> ctz32(msk); in shpc_get_status()169 pci_word_test_and_set_mask(status, value << ctz32(msk)); in shpc_set_status()
121 irq = ctz32(val); in extioi_enable_irq()129 irq = ctz32(val); in extioi_enable_irq()149 cpu = ctz32(cpu); in extioi_update_sw_coremap()183 ipnum = ctz32(ipnum); in extioi_update_sw_ipmap()241 irq = ctz32(old_data); in extioi_writew()245 irq = ctz32(old_data); in extioi_writew()
38 zeroes = ctz32(s->irq_pending[i] & ~s->mask[i]); in aw_a10_pic_update()
194 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); in or1200_initfn()196 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); in or1200_initfn()213 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); in openrisc_any_initfn()215 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); in openrisc_any_initfn()
156 boff = offset >> (ctz32(pfl->bank_width) + in pflash_cfi_query()157 ctz32(pfl->max_device_width) - ctz32(pfl->device_width)); in pflash_cfi_query()216 boff = offset >> (ctz32(pfl->bank_width) + in pflash_devid_query()217 ctz32(pfl->max_device_width) - ctz32(pfl->device_width)); in pflash_devid_query()757 pfl->cfi_table[0x27] = ctz32(device_len); /* + 1; */ in pflash_cfi01_fill_cfi_table()
216 qemu_icache_linesize_log = ctz32(isize); in init_cache_info()218 qemu_dcache_linesize_log = ctz32(dsize); in init_cache_info()
131 while ((ln = ctz32(diff)) != 32) { in omap_gpio_write()143 while ((ln = ctz32(diff)) != 32) { in omap_gpio_write()253 while ((ln = ctz32(diff)) != 32) { in omap2_gpio_module_out_update()443 while ((ln = ctz32(diff)) != 32) { in omap2_gpio_module_write()
90 line = ctz32(diff); in pcf8574_tx()
101 line = ctz32(diff); in max7310_tx()
71 bit = ctz32(diff); in scoop_gpio_handler_update()
187 return (be32_to_cpu(word) & mask) >> ctz32(mask); in xive_get_field32()194 (be32_to_cpu(word) & ~mask) | ((value << ctz32(mask)) & mask); in xive_set_field32()
118 uint32_t n = ctz32(windowstart) + 1; in HELPER()127 switch (ctz32(windowstart >> n)) { in HELPER()
236 static inline int ctz32(uint32_t val) in ctz32() function249 return ctz32(~val); in cto32()689 # define ctzl ctz32
164 return ctz32(size); in size_memop()
118 return arg ? ctz32(arg) : zero_val; in HELPER()
186 int slot = ctz32(slots); in acpi_pcihp_eject_slot()452 slot = ctz32(data); in pci_write()
50 len = ctz32(streaming_vec_reg_size(s)) - esz; in get_tile_rowcol()77 pos = esz + ctz32(sizeof(ARMVectorReg)); in get_tile_rowcol()
27 int r = ctz32(div); in msf2_divbits()
200 addr_bottom = addr_bottom + ctz32(bas); in check_watchpoint_in_range()
64 spd[3] = ctz32(rows) - spd[4]; in fix_spd_data()
144 int s = ctz32(nubus->slot_available_mask); in nubus_check_address()