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Searched refs:hierarchy (Results 1 – 16 of 16) sorted by relevance

/qemu/hw/acpi/
H A Dhmat.c99 assert(!(hmat_lb->hierarchy >> 4)); in build_hmat_lb()
100 build_append_int_noprefix(table_data, hmat_lb->hierarchy, 1); in build_hmat_lb()
204 int i, hierarchy, type, cache_level, total_levels; in hmat_build_table_structs() local
237 for (hierarchy = HMAT_LB_MEM_MEMORY; in hmat_build_table_structs()
238 hierarchy <= HMAT_LB_MEM_CACHE_3RD_LEVEL; hierarchy++) { in hmat_build_table_structs()
241 hmat_lb = numa_state->hmat_lb[hierarchy][type]; in hmat_build_table_structs()
/qemu/docs/
H A Dpcie.txt77 2.2 PCI Express only hierarchy
87 to keep a simple flat hierarchy that is enough for most scenarios.
133 2.3 PCI only hierarchy
188 if devices with IO BARs are used in the PCI Express hierarchy. Using the
190 PCI Express devices within PCI Express hierarchy.
193 without using IO ports. The PCI hierarchy has no such limitations.
202 Each element of the PCI Express hierarchy (Root Complexes,
210 Express hierarchy) enables the hierarchy to not spend bus numbers on
242 (1) PCI hierarchy
254 (2) PCI Express hierarchy:
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H A Dpci_expander_bridge.txt49 …owever, the bus behind is exposed through ACPI as a primary PCI bus and starts a new PCI hierarchy.
/qemu/include/sysemu/
H A Dnuma.h64 uint8_t hierarchy; member
/qemu/hw/core/
H A Dnuma.c215 numa_state->hmat_lb[node->hierarchy][node->data_type]; in parse_numa_hmat_lb()
244 numa_state->hmat_lb[node->hierarchy][node->data_type] = hmat_lb; in parse_numa_hmat_lb()
247 hmat_lb->hierarchy = node->hierarchy; in parse_numa_hmat_lb()
/qemu/docs/devel/
H A Dvirtio-backends.rst44 The author may decide to have a more expansive class hierarchy to
86 follow the normal hierarchy. Instead the a standalone object is based
H A Dreset.rst271 to follow the bus hierarchy; for a bus, it calls the function on every child
279 hierarchy changes.
281 The reset hierarchy is supposed to be static and built during machine creation.
300 removed in the bus hierarchy. At the moment, it occurs only in the raspi
H A Dclocks.rst145 input nor an output of a device. After the whole QOM hierarchy of the
H A Dmulti-process.rst209 The remote emulation process will run the QEMU object hierarchy without
513 request climbs the device's bus object hierarchy until the point where a
/qemu/docs/specs/
H A Dfsi.rst47 The LBUS is modelled to maintain the qdev bus hierarchy and to take advantages
H A Dppc-spapr-numa.rst22 physical hierarchy of the platform, as one or more lists that starts
144 provides a common-performance hierarchy, and the ibm,associativity-reference-points
/qemu/docs/system/devices/
H A Dcxl.rst101 are identical to those used for other parts of the CXL hierarchy
122 virtual hierarchy. Whilst more complex devices exist, their
/qemu/docs/system/s390x/
H A Dcpu-topology.rst8 tree-shaped hierarchy.
/qemu/docs/system/i386/
H A Dsgx.rst67 key hierarchy are bound to the physical platform. However live migration
/qemu/qapi/
H A Dmachine.json670 # The memory hierarchy in the System Locality Latency and Bandwidth
729 # @hierarchy: the Memory Hierarchy. Indicates the performance of
747 'hierarchy': 'HmatLBMemoryHierarchy',
/qemu/
H A Dqemu-options.hx321 CPU topology hierarchy must be equal to the maximum number of CPUs.
329 for a particular machine type board, an expected topology hierarchy can
339 For example, the following sub-option defines a CPU topology hierarchy
349 The following sub-option defines a CPU topology hierarchy (2 sockets
359 The following sub-option defines a CPU topology hierarchy (2 sockets
403 ``-numa hmat-lb,initiator=node,target=node,hierarchy=hierarchy,data-type=type[,latency=lat][,bandwi…
504 In '\ ``hmat-lb``\ ' option, node are NUMA node IDs. hierarchy is
505 the memory hierarchy of the target NUMA node: if hierarchy is
507 hierarchy is 'first-level\|second-level\|third-level', this
510 this structure instance: if 'hierarchy' is 'memory', 'data-type' is
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