Searched refs:hierarchy (Results 1 – 16 of 16) sorted by relevance
/qemu/hw/acpi/ |
H A D | hmat.c | 99 assert(!(hmat_lb->hierarchy >> 4)); in build_hmat_lb() 100 build_append_int_noprefix(table_data, hmat_lb->hierarchy, 1); in build_hmat_lb() 204 int i, hierarchy, type, cache_level, total_levels; in hmat_build_table_structs() local 237 for (hierarchy = HMAT_LB_MEM_MEMORY; in hmat_build_table_structs() 238 hierarchy <= HMAT_LB_MEM_CACHE_3RD_LEVEL; hierarchy++) { in hmat_build_table_structs() 241 hmat_lb = numa_state->hmat_lb[hierarchy][type]; in hmat_build_table_structs()
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/qemu/docs/ |
H A D | pcie.txt | 77 2.2 PCI Express only hierarchy 87 to keep a simple flat hierarchy that is enough for most scenarios. 133 2.3 PCI only hierarchy 188 if devices with IO BARs are used in the PCI Express hierarchy. Using the 190 PCI Express devices within PCI Express hierarchy. 193 without using IO ports. The PCI hierarchy has no such limitations. 202 Each element of the PCI Express hierarchy (Root Complexes, 210 Express hierarchy) enables the hierarchy to not spend bus numbers on 242 (1) PCI hierarchy 254 (2) PCI Express hierarchy: [all …]
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H A D | pci_expander_bridge.txt | 49 …owever, the bus behind is exposed through ACPI as a primary PCI bus and starts a new PCI hierarchy.
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/qemu/include/sysemu/ |
H A D | numa.h | 64 uint8_t hierarchy; member
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/qemu/hw/core/ |
H A D | numa.c | 215 numa_state->hmat_lb[node->hierarchy][node->data_type]; in parse_numa_hmat_lb() 244 numa_state->hmat_lb[node->hierarchy][node->data_type] = hmat_lb; in parse_numa_hmat_lb() 247 hmat_lb->hierarchy = node->hierarchy; in parse_numa_hmat_lb()
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/qemu/docs/devel/ |
H A D | virtio-backends.rst | 44 The author may decide to have a more expansive class hierarchy to 86 follow the normal hierarchy. Instead the a standalone object is based
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H A D | reset.rst | 271 to follow the bus hierarchy; for a bus, it calls the function on every child 279 hierarchy changes. 281 The reset hierarchy is supposed to be static and built during machine creation. 300 removed in the bus hierarchy. At the moment, it occurs only in the raspi
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H A D | clocks.rst | 145 input nor an output of a device. After the whole QOM hierarchy of the
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H A D | multi-process.rst | 209 The remote emulation process will run the QEMU object hierarchy without 513 request climbs the device's bus object hierarchy until the point where a
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/qemu/docs/specs/ |
H A D | fsi.rst | 47 The LBUS is modelled to maintain the qdev bus hierarchy and to take advantages
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H A D | ppc-spapr-numa.rst | 22 physical hierarchy of the platform, as one or more lists that starts 144 provides a common-performance hierarchy, and the ibm,associativity-reference-points
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/qemu/docs/system/devices/ |
H A D | cxl.rst | 101 are identical to those used for other parts of the CXL hierarchy 122 virtual hierarchy. Whilst more complex devices exist, their
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/qemu/docs/system/s390x/ |
H A D | cpu-topology.rst | 8 tree-shaped hierarchy.
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/qemu/docs/system/i386/ |
H A D | sgx.rst | 67 key hierarchy are bound to the physical platform. However live migration
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/qemu/qapi/ |
H A D | machine.json | 670 # The memory hierarchy in the System Locality Latency and Bandwidth 729 # @hierarchy: the Memory Hierarchy. Indicates the performance of 747 'hierarchy': 'HmatLBMemoryHierarchy',
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/qemu/ |
H A D | qemu-options.hx | 321 CPU topology hierarchy must be equal to the maximum number of CPUs. 329 for a particular machine type board, an expected topology hierarchy can 339 For example, the following sub-option defines a CPU topology hierarchy 349 The following sub-option defines a CPU topology hierarchy (2 sockets 359 The following sub-option defines a CPU topology hierarchy (2 sockets 403 ``-numa hmat-lb,initiator=node,target=node,hierarchy=hierarchy,data-type=type[,latency=lat][,bandwi… 504 In '\ ``hmat-lb``\ ' option, node are NUMA node IDs. hierarchy is 505 the memory hierarchy of the target NUMA node: if hierarchy is 507 hierarchy is 'first-level\|second-level\|third-level', this 510 this structure instance: if 'hierarchy' is 'memory', 'data-type' is [all …]
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