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Searched refs:idr (Results 1 – 8 of 8) sorted by relevance

/qemu/hw/arm/
H A Dsmmuv3.c261 s->idr[0] = FIELD_DP32(s->idr[0], IDR0, S2P, 1); in smmuv3_init_regs()
263 s->idr[0] = FIELD_DP32(s->idr[0], IDR0, S1P, 1); in smmuv3_init_regs()
273 s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TERM_MODEL, 1); in smmuv3_init_regs()
275 s->idr[0] = FIELD_DP32(s->idr[0], IDR0, STLEVEL, 1); in smmuv3_init_regs()
281 s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, 1); in smmuv3_init_regs()
284 s->idr[3] = FIELD_DP32(s->idr[3], IDR3, XNX, 1); in smmuv3_init_regs()
286 s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1); in smmuv3_init_regs()
287 s->idr[3] = FIELD_DP32(s->idr[3], IDR3, BBML, 2); in smmuv3_init_regs()
291 s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1); in smmuv3_init_regs()
292 s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN16K, 1); in smmuv3_init_regs()
[all …]
/qemu/include/hw/arm/
H A Dsmmuv3.h42 uint32_t idr[6]; member
87 #define STAGE1_SUPPORTED(s) FIELD_EX32(s->idr[0], IDR0, S1P)
88 #define STAGE2_SUPPORTED(s) FIELD_EX32(s->idr[0], IDR0, S2P)
/qemu/hw/gpio/
H A Dstm32l4x5_gpio.c82 s->idr = 0x00000000; in stm32l4x5_gpio_reset_hold()
124 uint32_t old_idr = s->idr; in update_gpio_idr()
182 s->idr = (old_idr & ~new_idr_mask) | (new_idr & new_idr_mask); in update_gpio_idr()
183 trace_stm32l4x5_gpio_update_idr(s->name, old_idr, s->idr); in update_gpio_idr()
360 return s->idr; in stm32l4x5_gpio_read()
437 VMSTATE_UINT32(idr, Stm32l4x5GpioState),
/qemu/tests/qtest/
H A Dstm32l4x5_gpio-test.c222 uint32_t idr = gpio_readl(GPIO_A, IDR); in test_idr_reset_value() local
231 g_assert_cmphex(idr, ==, reset(GPIO_A, IDR)); in test_idr_reset_value()
237 idr = gpio_readl(GPIO_B, IDR); in test_idr_reset_value()
246 g_assert_cmphex(idr, ==, reset(GPIO_B, IDR)); in test_idr_reset_value()
252 idr = gpio_readl(GPIO_C, IDR); in test_idr_reset_value()
260 g_assert_cmphex(idr, ==, reset(GPIO_C, IDR)); in test_idr_reset_value()
266 idr = gpio_readl(GPIO_H, IDR); in test_idr_reset_value()
274 g_assert_cmphex(idr, ==, reset(GPIO_H, IDR)); in test_idr_reset_value()
/qemu/hw/misc/
H A Daspeed_lpc.c74 int idr; member
82 .idr = IDR1,
89 .idr = IDR2,
96 .idr = IDR3,
103 .idr = IDR4,
/qemu/hw/intc/
H A Dopenpic.c429 return opp->src[n_IRQ].idr; in read_IRQreg_idr()
460 src->idr = val & mask; in write_IRQreg_idr()
461 DPRINTF("Set IDR %d to 0x%08x", n_IRQ, src->idr); in write_IRQreg_idr()
464 if (src->idr & crit_mask) { in write_IRQreg_idr()
465 if (src->idr & normal_mask) { in write_IRQreg_idr()
477 if (src->idr & (1UL << n_ci)) { in write_IRQreg_idr()
484 src->destmask = src->idr & normal_mask; in write_IRQreg_idr()
487 src->destmask = src->idr; in write_IRQreg_idr()
497 DPRINTF("Set ILR %d to 0x%08x, output %d", n_IRQ, src->idr, in write_IRQreg_ilr()
1423 VMSTATE_UINT32(idr, IRQSource),
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/qemu/include/hw/gpio/
H A Dstm32l4x5_gpio.h41 uint32_t idr; member
/qemu/include/hw/ppc/
H A Dopenpic.h69 uint32_t idr; /* IRQ destination register */ member