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Searched refs:mcause (Results 1 – 5 of 5) sorted by relevance

/qemu/target/riscv/
H A Dmachine.c396 VMSTATE_UINTTL(env.mcause, RISCVCPU),
H A Dcpu.h255 target_ulong mcause; member
H A Dcpu_helper.c1826 env->mcause = cause | ~(((target_ulong)-1) >> async); in riscv_cpu_do_interrupt()
H A Dcsr.c2050 *val = env->mcause; in read_mcause()
2057 env->mcause = val; in write_mcause()
H A Dcpu.c964 env->mcause = 0; in riscv_cpu_reset_hold()