Searched refs:misa_mxl (Results 1 – 5 of 5) sorted by relevance
/qemu/target/riscv/ |
H A D | cpu.h | 190 uint32_t misa_mxl; /* current mxl */ member 584 return env->misa_mxl; 607 RISCVMXL xl = env->misa_mxl; in cpu_get_xl() 638 return env->misa_mxl; in cpu_recompute_xl() 669 return env->misa_mxl; in riscv_cpu_sxl()
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H A D | cpu.c | 943 env->misa_mxl = mcc->misa_mxl_max; in riscv_cpu_reset_hold() 946 if (env->misa_mxl > MXL_RV32) { in riscv_cpu_reset_hold() 951 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); in riscv_cpu_reset_hold() 952 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); in riscv_cpu_reset_hold() 955 MSTATUS64_SXL, env->misa_mxl); in riscv_cpu_reset_hold() 957 MSTATUS64_UXL, env->misa_mxl); in riscv_cpu_reset_hold() 959 MSTATUS64_SXL, env->misa_mxl); in riscv_cpu_reset_hold() 961 MSTATUS64_UXL, env->misa_mxl); in riscv_cpu_reset_hold() 1231 if (cpu->env.misa_mxl == MXL_RV32) { in riscv_add_satp_mode_properties() 1325 env->misa_mxl = mcc->misa_mxl_max; in riscv_cpu_init()
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H A D | machine.c | 372 VMSTATE_UINT32(env.misa_mxl, RISCVCPU),
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H A D | csr.c | 1446 switch (env->misa_mxl) { in read_misa()
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/qemu/target/riscv/tcg/ |
H A D | tcg-cpu.c | 1070 if (cpu->env.misa_mxl != MXL_RV64) { in cpu_set_profile() 1329 if (env->misa_mxl != MXL_RV32) { in riscv_init_max_cpu_extensions()
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