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/qemu/tests/tcg/hexagon/
H A Dmem_noshuf.c208 res32 = mem_noshuf_sb_lb(&n.b[0], &n.b[0], 0x87); in main()
212 res32 = mem_noshuf_sb_lub(&n.b[0], &n.ub[0], 0x87); in main()
216 res32 = mem_noshuf_sb_lh(&n.b[0], &n.h[0], 0x87); in main()
224 res32 = mem_noshuf_sb_lw(&n.b[0], &n.w[0], 0x87); in main()
228 res64 = mem_noshuf_sb_ld(&n.b[0], &n.d[0], 0x87); in main()
346 res32 = mem_noshuf_sb_lb(&n.b[1], &n.b[0], 0x87); in main()
350 res32 = mem_noshuf_sb_lb(&n.b[0], &n.b[1], 0x87); in main()
400 res64 = pred_ld_sd(false, &n.d[0], &n.d[0], in main()
406 res64 = pred_ld_sd(true, &n.d[0], &n.d[0], in main()
412 res64 = pred_ld_sd_pi(false, &n.d[0], &n.d[0], in main()
[all …]
/qemu/configs/devices/arm-softmmu/
H A Ddefault.mak9 # CONFIG_ARM_VIRT=n
14 # CONFIG_EXYNOS4=n
19 # CONFIG_MPS3R=n
20 # CONFIG_MUSCA=n
22 # CONFIG_SX1=n
30 # CONFIG_ZYNQ=n
33 # CONFIG_SPITZ=n
34 # CONFIG_TOSA=n
35 # CONFIG_Z2=n
42 # CONFIG_MPS2=n
[all …]
/qemu/hw/net/
H A Dvirtio-net.c626 memcpy(&n->mac[0], &n->nic->conf->macaddr, sizeof(n->mac)); in virtio_net_reset()
949 .n = n, in failover_find_primary_device()
1683 VirtIONet *n = q->n; in virtio_net_has_buffers() local
2627 chain->n = n; in virtio_net_rsc_lookup_chain()
2723 VirtIONet *n = q->n; in virtio_net_flush_tx() local
2876 VirtIONet *n = q->n; in virtio_net_tx_timer() local
2926 VirtIONet *n = q->n; in virtio_net_tx_bh() local
2995 n->vqs[index].n = n; in virtio_net_add_queue()
3736 n->tx_timeout = n->net_conf.txtimer; in virtio_net_device_realize()
3755 memcpy(&n->mac[0], &n->nic_conf.macaddr, sizeof(n->mac)); in virtio_net_device_realize()
[all …]
/qemu/tests/unit/
H A Dtest-aio.c26 int n; member
43 int n; member
50 int n; member
59 if (++data->n < data->max) { in bh_test_cb()
67 if (++data->n < data->max) { in timer_test_cb()
80 if (++data->n < data->max) { in bh_delete_cb()
92 data->n++; in event_ready_cb()
139 while (data.n < 10) { in test_bh_schedule10()
337 data.n = 0; in test_wait_event_notifier_noflush()
668 data.n = 0; in test_source_wait_event_notifier_noflush()
[all …]
/qemu/roms/
H A Dconfig.seabios-128k5 CONFIG_ATA_DMA=n
6 CONFIG_XEN=n
7 CONFIG_ATA_PIO32=n
8 CONFIG_AHCI=n
9 CONFIG_SDCARD=n
12 CONFIG_PVSCSI=n
15 CONFIG_MEGASAS=n
17 CONFIG_NVME=n
18 CONFIG_USE_SMM=n
21 CONFIG_USB=n
[all …]
H A Dconfig.seabios-microvm5 CONFIG_XEN=n
7 CONFIG_ATA=n
8 CONFIG_AHCI=n
9 CONFIG_SDCARD=n
10 CONFIG_PVSCSI=n
11 CONFIG_ESP_SCSI=n
13 CONFIG_MEGASAS=n
15 CONFIG_FLOPPY=n
17 CONFIG_NVME=n
19 CONFIG_USB=n
[all …]
/qemu/configs/devices/i386-softmmu/
H A Ddefault.mak5 #CONFIG_AMD_IOMMU=n
6 #CONFIG_APPLESMC=n
7 #CONFIG_FDC=n
8 #CONFIG_HPET=n
9 #CONFIG_HYPERV=n
18 #CONFIG_QXL=n
19 #CONFIG_SEV=n
20 #CONFIG_SGA=n
24 #CONFIG_VTD=n
25 #CONFIG_SGX=n
[all …]
/qemu/target/cris/
H A Dgdbstub.c28 if (n < 15) { in crisv10_cpu_gdb_read_register()
32 if (n == 15) { in crisv10_cpu_gdb_read_register()
36 if (n < 32) { in crisv10_cpu_gdb_read_register()
61 if (n < 16) { in cris_cpu_gdb_read_register()
65 if (n >= 21 && n < 32) { in cris_cpu_gdb_read_register()
68 if (n >= 33 && n < 49) { in cris_cpu_gdb_read_register()
71 switch (n) { in cris_cpu_gdb_read_register()
94 if (n > 49) { in cris_cpu_gdb_write_register()
100 if (n < 16) { in cris_cpu_gdb_write_register()
104 if (n >= 21 && n < 32) { in cris_cpu_gdb_write_register()
[all …]
/qemu/target/loongarch/
H A Dgdbstub.c39 if (0 <= n && n < 32) { in loongarch_cpu_gdb_read_register()
40 val = env->gpr[n]; in loongarch_cpu_gdb_read_register()
41 } else if (n == 32) { in loongarch_cpu_gdb_read_register()
44 } else if (n == 33) { in loongarch_cpu_gdb_read_register()
46 } else if (n == 34) { in loongarch_cpu_gdb_read_register()
50 if (0 <= n && n <= 34) { in loongarch_cpu_gdb_read_register()
75 if (0 <= n && n < 32) { in loongarch_cpu_gdb_write_register()
90 if (0 <= n && n < 32) { in loongarch_gdb_get_fpu()
92 } else if (32 <= n && n < 40) { in loongarch_gdb_get_fpu()
106 if (0 <= n && n < 32) { in loongarch_gdb_set_fpu()
[all …]
/qemu/target/hexagon/
H A Dgdbstub.c27 if (n == HEX_REG_P3_0_ALIASED) { in hexagon_gdb_read_register()
35 if (n < TOTAL_PER_THREAD_REGS) { in hexagon_gdb_read_register()
46 if (n == HEX_REG_P3_0_ALIASED) { in hexagon_gdb_write_register()
54 if (n < TOTAL_PER_THREAD_REGS) { in hexagon_gdb_write_register()
55 env->gpr[n] = ldtul_p(mem_buf); in hexagon_gdb_write_register()
87 if (n < NUM_VREGS) { in hexagon_hvx_gdb_read_register()
90 n -= NUM_VREGS; in hexagon_hvx_gdb_read_register()
92 if (n < NUM_QREGS) { in hexagon_hvx_gdb_read_register()
124 if (n < NUM_VREGS) { in hexagon_hvx_gdb_write_register()
127 n -= NUM_VREGS; in hexagon_hvx_gdb_write_register()
[all …]
/qemu/scripts/coccinelle/
H A Duse-g_new-etc.cocci24 expression n;
27 +g_new(T, n)
30 expression n;
33 +g_try_new(T, n)
36 expression n;
39 +g_new0(T, n)
42 expression n;
60 expression n;
63 +g_new(T, n)
66 expression n;
[all …]
/qemu/target/ppc/
H A Dgdbstub.c28 switch (n) { in ppc_gdb_register_len_apple()
53 switch (n) { in ppc_gdb_register_len()
119 if (n < 32) { in ppc_cpu_gdb_read_register()
162 if (n < 32) { in ppc_cpu_gdb_read_register_apple()
214 if (n < 32) { in ppc_cpu_gdb_write_register()
260 if (n < 32) { in ppc_cpu_gdb_write_register_apple()
445 if (n < 32) { in gdb_get_float_reg()
465 if (n < 32) { in gdb_set_float_reg()
484 if (n < 32) { in gdb_get_avr_reg()
511 if (n < 32) { in gdb_set_avr_reg()
[all …]
/qemu/target/sparc/
H A Dgdbstub.c34 if (n < 8) { in sparc_cpu_gdb_read_register()
38 if (n < 32) { in sparc_cpu_gdb_read_register()
43 if (n < 64) { in sparc_cpu_gdb_read_register()
45 if (n & 1) { in sparc_cpu_gdb_read_register()
52 switch (n) { in sparc_cpu_gdb_read_register()
73 if (n < 64) { in sparc_cpu_gdb_read_register()
75 if (n & 1) { in sparc_cpu_gdb_read_register()
81 if (n < 80) { in sparc_cpu_gdb_read_register()
85 switch (n) { in sparc_cpu_gdb_read_register()
120 if (n < 8) { in sparc_cpu_gdb_write_register()
[all …]
/qemu/hw/i386/kvm/
H A Dxenstore_impl.c109 n->ref = 1; in xs_node_new()
115 return n; in xs_node_new()
124 n->ref++; in xs_node_ref()
125 return n; in xs_node_ref()
130 if (!n) { in xs_node_unref()
152 g_free(n); in xs_node_unref()
195 return n; in xs_node_create()
228 return n; in xs_node_copy()
450 return n; in xs_node_copy_deleted()
474 *n = NULL; in xs_node_rm()
[all …]
/qemu/hw/nvme/
H A Dctrl.c519 lo = n->params.legacy_cmb ? n->cmb.mem.addr : n->cmb.cba; in nvme_addr_is_cmb()
527 hwaddr base = n->params.legacy_cmb ? n->cmb.mem.addr : n->cmb.cba; in nvme_addr_to_cmb()
574 if (n->bar.cmbsz && nvme_addr_is_cmb(n, addr) && nvme_addr_is_cmb(n, hi)) { in nvme_addr_read()
5364 return nvme_c2h(n, (uint8_t *)&n->id_ctrl, sizeof(n->id_ctrl), req); in nvme_identify_ctrl()
7108 nvme_free_sq(n->sq[i], n); in nvme_ctrl_reset()
7113 nvme_free_cq(n->cq[i], n); in nvme_ctrl_reset()
7320 n->bar.intmc = n->bar.intms; in nvme_write_bar()
7333 n->bar.intmc = n->bar.intms; in nvme_write_bar()
7983 memory_region_init_io(&n->cmb.mem, OBJECT(n), &nvme_cmb_ops, n, in nvme_init_cmb()
8296 n->bar.intmc = n->bar.intms = 0; in nvme_init_ctrl()
[all …]
/qemu/crypto/
H A Dclmul.c11 uint64_t clmul_8x8_low(uint64_t n, uint64_t m) in clmul_8x8_low() argument
19 n >>= 1; in clmul_8x8_low()
31 n >>= 1; in clmul_8x4_even_int()
39 n &= 0x00ff00ff00ff00ffull; in clmul_8x4_even()
41 return clmul_8x4_even_int(n, m); in clmul_8x4_even()
46 return clmul_8x4_even(n >> 8, m >> 8); in clmul_8x4_odd()
66 n &= 0x0000ffff0000ffffull; in clmul_16x2_even()
72 n >>= 1; in clmul_16x2_even()
89 r ^= n & 1 ? m : 0; in clmul_32()
90 n >>= 1; in clmul_32()
[all …]
/qemu/target/s390x/
H A Dgdbstub.c35 switch (n) { in s390_cpu_gdb_read_register()
51 switch (n) { in s390_cpu_gdb_write_register()
76 switch (n) { in cpu_read_ac_reg()
89 switch (n) { in cpu_write_ac_reg()
109 switch (n) { in cpu_read_fp_reg()
124 switch (n) { in cpu_write_fp_reg()
148 switch (n) { in cpu_read_vreg()
168 switch (n) { in cpu_write_vreg()
191 switch (n) { in cpu_read_c_reg()
204 switch (n) { in cpu_write_c_reg()
[all …]
/qemu/util/
H A Dqdist.c23 dist->n = 0; in qdist_init()
53 if (dist->n) { in qdist_add()
69 dist->n++; in qdist_add()
175 if (n == 0 || from->n == 1) { in qdist_bin__internal()
176 n = from->n; in qdist_bin__internal()
184 if (n == from->n) { in qdist_bin__internal()
193 to->n = from->n; in qdist_bin__internal()
255 double n; in qdist_pr_label() local
266 n = n_bins ? n_bins : dist->n; in qdist_pr_label()
350 return dist->n; in qdist_unique_entries()
[all …]
/qemu/hw/arm/
H A Dexynos4210.c344 for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { in exynos4210_init_board_irqs()
499 for (n = 0; n < ARRAY_SIZE(smpboot); n++) { in exynos4210_write_secondary()
556 for (n = 0; n < EXYNOS4210_NCPUS; n++) { in exynos4210_realize()
592 for (n = 0; n < EXYNOS4210_NCPUS; n++) { in exynos4210_realize()
608 for (n = 0; n < EXYNOS4210_NCPUS; n++) { in exynos4210_realize()
616 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { in exynos4210_realize()
626 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { in exynos4210_realize()
688 for (n = 0; n < 4; n++) { in exynos4210_realize()
701 for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) { in exynos4210_realize()
738 for (n = 0; n < EXYNOS4210_SDHCI_NUMBER; n++) { in exynos4210_realize()
[all …]
H A Dbcm2838.c88 for (int n = 0; n < bc_base->core_count; n++) { in bcm2838_realize() local
98 object_property_set_bool(OBJECT(&s_base->cpu[n].core), in bcm2838_realize()
140 for (int n = 0; n < BCM283X_NCPUS; n++) { in bcm2838_realize() local
141 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 4 + n, in bcm2838_realize()
143 + GIC_VIFACE_OTHER_OFS(n)); in bcm2838_realize()
148 for (int n = 0; n < BCM283X_NCPUS; n++) { in bcm2838_realize() local
149 DeviceState *cpudev = DEVICE(&s_base->cpu[n]); in bcm2838_realize()
152 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), n, in bcm2838_realize()
209 for (int n = GIC_SPI_INTERRUPT_DMA_0; n <= GIC_SPI_INTERRUPT_DMA_6; n++) { in bcm2838_realize() local
211 n - GIC_SPI_INTERRUPT_DMA_0, in bcm2838_realize()
[all …]
/qemu/hw/core/
H A Dsysbus.c127 return (n < dev->num_mmio); in sysbus_has_mmio()
133 assert(n >= 0 && n < dev->num_mmio); in sysbus_mmio_map_common()
143 dev->mmio[n].addr = addr; in sysbus_mmio_map_common()
159 assert(n >= 0 && n < dev->num_mmio); in sysbus_mmio_unmap()
192 int n; in sysbus_init_mmio() local
195 n = dev->num_mmio++; in sysbus_init_mmio()
196 dev->mmio[n].addr = -1; in sysbus_init_mmio()
202 assert(n >= 0 && n < QDEV_MAX_MMIO); in sysbus_mmio_get_region()
232 int n; in sysbus_create_varargs() local
241 n = 0; in sysbus_create_varargs()
[all …]
H A Dgpio.c53 opaque, n); in qdev_init_gpio_in_named_with_opaque()
66 gpio_list->num_in += n; in qdev_init_gpio_in_named_with_opaque()
71 qdev_init_gpio_in_named(dev, handler, NULL, n); in qdev_init_gpio_in()
85 memset(pins, 0, sizeof(*pins) * n); in qdev_init_gpio_out_named()
86 for (i = 0; i < n; ++i) { in qdev_init_gpio_out_named()
96 gpio_list->num_out += n; in qdev_init_gpio_out_named()
101 qdev_init_gpio_out_named(dev, pins, NULL, n); in qdev_init_gpio_out()
108 assert(n >= 0 && n < gpio_list->num_in); in qdev_get_gpio_in_named()
109 return gpio_list->in[n]; in qdev_get_gpio_in_named()
112 qemu_irq qdev_get_gpio_in(DeviceState *dev, int n) in qdev_get_gpio_in() argument
[all …]
/qemu/include/hw/cxl/
H A Dcxl_component.h124 #define HDM_DECODER_INIT(n) \ argument
125 REG32(CXL_HDM_DECODER##n##_BASE_LO, \
126 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x10) \
127 FIELD(CXL_HDM_DECODER##n##_BASE_LO, L, 28, 4) \
128 REG32(CXL_HDM_DECODER##n##_BASE_HI, \
129 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x14) \
130 REG32(CXL_HDM_DECODER##n##_SIZE_LO, \
131 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x18) \
132 REG32(CXL_HDM_DECODER##n##_SIZE_HI, \
133 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x1C) \
[all …]
/qemu/target/mips/
H A Dgdbstub.c30 if (n < 32) { in mips_cpu_gdb_read_register()
33 if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) { in mips_cpu_gdb_read_register()
34 switch (n) { in mips_cpu_gdb_read_register()
49 switch (n) { in mips_cpu_gdb_read_register()
68 if (n > 89) { in mips_cpu_gdb_read_register()
85 if (n < 32) { in mips_cpu_gdb_write_register()
86 env->active_tc.gpr[n] = tmp; in mips_cpu_gdb_write_register()
89 if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) { in mips_cpu_gdb_write_register()
90 switch (n) { in mips_cpu_gdb_write_register()
109 switch (n) { in mips_cpu_gdb_write_register()
[all …]
/qemu/tests/qtest/
H A Dnpcm7xx_gpio-test.c56 static void gpio_unlock(int n) in gpio_unlock() argument
58 if (readl(GPIO(n) + GP_N_TLOCK1) != 0) { in gpio_unlock()
65 static void gpio_reset(int n) in gpio_reset() argument
69 writel(GPIO(n) + GP_N_EVEN, 0x00000000); in gpio_reset()
71 writel(GPIO(n) + GP_N_POL, 0x00000000); in gpio_reset()
73 writel(GPIO(n) + GP_N_OE, 0x00000000); in gpio_reset()
75 writel(GPIO(n) + GP_N_PU, 0xffffffff); in gpio_reset()
76 writel(GPIO(n) + GP_N_PD, 0x00000000); in gpio_reset()
77 writel(GPIO(n) + GP_N_IEM, 0xffffffff); in gpio_reset()
312 intptr_t n = (intptr_t)test_data; in test_gpion_irq() local
[all …]

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