/qemu/tests/tcg/mips/user/ase/msa/ |
H A D | test_msa_compile_32r5eb.sh | 7 -EB -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \ 10 -EB -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \ 13 -EB -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \ 16 -EB -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \ 19 -EB -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \ 22 -EB -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \ 25 -EB -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \ 28 -EB -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \ 31 -EB -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \ 34 -EB -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \ [all …]
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H A D | test_msa_compile_32r5el.sh | 7 -EL -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \ 10 -EL -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \ 13 -EL -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \ 16 -EL -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \ 19 -EL -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \ 22 -EL -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \ 25 -EL -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \ 28 -EL -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \ 31 -EL -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \ 34 -EL -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \ [all …]
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/qemu/tests/tcg/s390x/ |
H A D | pgm-specification.mak | 5 br-odd \ 9 ex-odd \
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/qemu/target/hexagon/ |
H A D | arch.h | 27 uint64_t interleave(uint32_t odd, uint32_t even);
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H A D | arch.c | 128 uint64_t interleave(uint32_t odd, uint32_t even) in interleave() argument 131 uint64_t myodd = odd; in interleave()
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/qemu/hw/ppc/ |
H A D | prep.c | 154 int odd; in NVRAM_compute_crc() local 156 odd = count & 1; in NVRAM_compute_crc() 161 if (odd) { in NVRAM_compute_crc()
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/qemu/target/riscv/insn_trans/ |
H A D | trans_rvzacas.c.inc | 81 * Encodings with odd numbered registers specified in rs2 and rd are 119 * Encodings with odd numbered registers specified in rs2 and rd are
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/qemu/target/loongarch/tcg/ |
H A D | tlb_helper.c | 551 void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd, in helper_ldpte() argument 593 if (odd) { in helper_ldpte() 607 phys = base | (odd ? ptoffset1 : ptoffset0); in helper_ldpte() 612 if (odd) { in helper_ldpte()
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/qemu/target/arm/tcg/ |
H A D | mte_helper.c | 703 static int checkN(uint8_t *mem, int odd, int cmp, int count) in checkN() argument 711 if (odd) { in checkN() 752 static int checkNrev(uint8_t *mem, int odd, int cmp, int count) in checkNrev() argument 760 if (!odd) { in checkNrev()
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H A D | vfp-uncond.decode | 30 # VFP registers have an odd encoding with a four-bit field
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H A D | vfp.decode | 30 # VFP registers have an odd encoding with a four-bit field
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H A D | sve_helper.c | 3176 l = compress_bits(n[0] >> odd, esz); in HELPER() 3177 h = compress_bits(m[0] >> odd, esz); in HELPER() 3190 l = compress_bits(l >> odd, esz); in HELPER() 3191 h = compress_bits(h >> odd, esz); in HELPER() 3205 l = compress_bits(l >> odd, esz); in HELPER() 3206 h = compress_bits(h >> odd, esz); in HELPER() 3212 l = compress_bits(l >> odd, esz); in HELPER() 3213 h = compress_bits(h >> odd, esz); in HELPER() 3218 l = compress_bits(l >> odd, esz); in HELPER() 3219 h = compress_bits(h >> odd, esz); in HELPER() [all …]
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H A D | neon-dp.decode | 99 # which does not have this odd reversed-operand situation.
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H A D | sve.decode | 1644 ### SVE2 floating-point convert precision odd elements
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/qemu/docs/devel/ |
H A D | maintainers.rst | 46 much other than throw the odd patch in.
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/qemu/target/hexagon/idef-parser/ |
H A D | parser-helpers.h | 281 HexValue *odd,
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/qemu/pc-bios/ |
H A D | petalogix-s3adsp1800.dts | 242 xlnx,odd-parity = <0x00>;
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/qemu/tests/qapi-schema/ |
H A D | meson.build | 270 # is GNU-diff only. The odd-looking python is because we must avoid
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/qemu/docs/specs/ |
H A D | rocker.txt | 135 Rx vector is odd 350 issue exists. In particular, buffers that start on odd-8-byte boundary and/or
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/qemu/fpu/ |
H A D | softfloat-parts.c.inc | 263 /* Need to recompute round-to-even/round-to-odd. */ 736 * If base-2 exponent is odd, exchange that for multiply by 2,
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/qemu/hw/net/ |
H A D | rtl8139.c | 1859 uint8_t odd[2] = {*data, 0}; in ones_complement_sum() local 1860 result += *(uint16_t*)odd; in ones_complement_sum()
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/qemu/target/hexagon/imported/ |
H A D | compare.idef | 208 "Pack the odd and even bits of two predicate registers",
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/qemu/target/loongarch/tcg/insn_trans/ |
H A D | trans_vec.c.inc | 624 /* Sign-extend the odd elements for vector */ 773 /* Sign-extend the odd elements for vector */ 935 /* Zero-extend the odd elements for vector */ 1097 /* Zero-extend the odd elements for vector */ 1267 /* Zero-extend the odd elements from a */ 1269 /* Sign-extend the odd elements from b */
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/qemu/target/i386/tcg/ |
H A D | emit.c.inc | 61 TCGv_i32 odd); 563 #define FMA_SSE_PACKED(uname, ptr0, ptr1, ptr2, even, odd) \ 572 tcg_constant_i32((even) ^ (odd))); \
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/qemu/target/hexagon/imported/mmvec/ |
H A D | ext.idef | 389 …ob, "Vxx32|=vunpackob(Vu32)", "Vxx32.h|=vunpacko(Vu32.b)", "Unpack byte to odd bytes ", fVAR… 390 …, "Vxx32|=vunpackoh(Vu32)", "Vxx32.w|=vunpacko(Vu32.h)", "Unpack halves to odd halves", fVARRA… 2220 … to choose next-bigger elements from vector, then use LSB from idx to choose odd or even element */
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