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Searched refs:odd (Results 1 – 25 of 31) sorted by relevance

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/qemu/tests/tcg/mips/user/ase/msa/
H A Dtest_msa_compile_32r5eb.sh7 -EB -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \
10 -EB -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \
13 -EB -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \
16 -EB -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \
19 -EB -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \
22 -EB -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \
25 -EB -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \
28 -EB -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \
31 -EB -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \
34 -EB -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \
[all …]
H A Dtest_msa_compile_32r5el.sh7 -EL -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \
10 -EL -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \
13 -EL -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \
16 -EL -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \
19 -EL -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \
22 -EL -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \
25 -EL -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \
28 -EL -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \
31 -EL -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \
34 -EL -static -mabi=32 -march=mips32r5 -mmsa -mno-odd-spreg -mfp64 -mnan=2008 -o \
[all …]
/qemu/tests/tcg/s390x/
H A Dpgm-specification.mak5 br-odd \
9 ex-odd \
/qemu/target/hexagon/
H A Darch.h27 uint64_t interleave(uint32_t odd, uint32_t even);
H A Darch.c128 uint64_t interleave(uint32_t odd, uint32_t even) in interleave() argument
131 uint64_t myodd = odd; in interleave()
/qemu/hw/ppc/
H A Dprep.c154 int odd; in NVRAM_compute_crc() local
156 odd = count & 1; in NVRAM_compute_crc()
161 if (odd) { in NVRAM_compute_crc()
/qemu/target/riscv/insn_trans/
H A Dtrans_rvzacas.c.inc81 * Encodings with odd numbered registers specified in rs2 and rd are
119 * Encodings with odd numbered registers specified in rs2 and rd are
/qemu/target/loongarch/tcg/
H A Dtlb_helper.c551 void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd, in helper_ldpte() argument
593 if (odd) { in helper_ldpte()
607 phys = base | (odd ? ptoffset1 : ptoffset0); in helper_ldpte()
612 if (odd) { in helper_ldpte()
/qemu/target/arm/tcg/
H A Dmte_helper.c703 static int checkN(uint8_t *mem, int odd, int cmp, int count) in checkN() argument
711 if (odd) { in checkN()
752 static int checkNrev(uint8_t *mem, int odd, int cmp, int count) in checkNrev() argument
760 if (!odd) { in checkNrev()
H A Dvfp-uncond.decode30 # VFP registers have an odd encoding with a four-bit field
H A Dvfp.decode30 # VFP registers have an odd encoding with a four-bit field
H A Dsve_helper.c3176 l = compress_bits(n[0] >> odd, esz); in HELPER()
3177 h = compress_bits(m[0] >> odd, esz); in HELPER()
3190 l = compress_bits(l >> odd, esz); in HELPER()
3191 h = compress_bits(h >> odd, esz); in HELPER()
3205 l = compress_bits(l >> odd, esz); in HELPER()
3206 h = compress_bits(h >> odd, esz); in HELPER()
3212 l = compress_bits(l >> odd, esz); in HELPER()
3213 h = compress_bits(h >> odd, esz); in HELPER()
3218 l = compress_bits(l >> odd, esz); in HELPER()
3219 h = compress_bits(h >> odd, esz); in HELPER()
[all …]
H A Dneon-dp.decode99 # which does not have this odd reversed-operand situation.
H A Dsve.decode1644 ### SVE2 floating-point convert precision odd elements
/qemu/docs/devel/
H A Dmaintainers.rst46 much other than throw the odd patch in.
/qemu/target/hexagon/idef-parser/
H A Dparser-helpers.h281 HexValue *odd,
/qemu/pc-bios/
H A Dpetalogix-s3adsp1800.dts242 xlnx,odd-parity = <0x00>;
/qemu/tests/qapi-schema/
H A Dmeson.build270 # is GNU-diff only. The odd-looking python is because we must avoid
/qemu/docs/specs/
H A Drocker.txt135 Rx vector is odd
350 issue exists. In particular, buffers that start on odd-8-byte boundary and/or
/qemu/fpu/
H A Dsoftfloat-parts.c.inc263 /* Need to recompute round-to-even/round-to-odd. */
736 * If base-2 exponent is odd, exchange that for multiply by 2,
/qemu/hw/net/
H A Drtl8139.c1859 uint8_t odd[2] = {*data, 0}; in ones_complement_sum() local
1860 result += *(uint16_t*)odd; in ones_complement_sum()
/qemu/target/hexagon/imported/
H A Dcompare.idef208 "Pack the odd and even bits of two predicate registers",
/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_vec.c.inc624 /* Sign-extend the odd elements for vector */
773 /* Sign-extend the odd elements for vector */
935 /* Zero-extend the odd elements for vector */
1097 /* Zero-extend the odd elements for vector */
1267 /* Zero-extend the odd elements from a */
1269 /* Sign-extend the odd elements from b */
/qemu/target/i386/tcg/
H A Demit.c.inc61 TCGv_i32 odd);
563 #define FMA_SSE_PACKED(uname, ptr0, ptr1, ptr2, even, odd) \
572 tcg_constant_i32((even) ^ (odd))); \
/qemu/target/hexagon/imported/mmvec/
H A Dext.idef389 …ob, "Vxx32|=vunpackob(Vu32)", "Vxx32.h|=vunpacko(Vu32.b)", "Unpack byte to odd bytes ", fVAR…
390 …, "Vxx32|=vunpackoh(Vu32)", "Vxx32.w|=vunpacko(Vu32.h)", "Unpack halves to odd halves", fVARRA…
2220 … to choose next-bigger elements from vector, then use LSB from idx to choose odd or even element */

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