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Searched refs:opc (Results 1 – 25 of 48) sorted by relevance

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/qemu/include/hw/xtensa/
H A Dxtensa-isa.h378 xtensa_insnbuf slotbuf, xtensa_opcode opc);
383 const char *xtensa_opcode_name(xtensa_isa isa, xtensa_opcode opc);
403 int xtensa_opcode_is_branch(xtensa_isa isa, xtensa_opcode opc);
405 int xtensa_opcode_is_jump(xtensa_isa isa, xtensa_opcode opc);
407 int xtensa_opcode_is_loop(xtensa_isa isa, xtensa_opcode opc);
409 int xtensa_opcode_is_call(xtensa_isa isa, xtensa_opcode opc);
418 int xtensa_opcode_num_operands(xtensa_isa isa, xtensa_opcode opc);
420 int xtensa_opcode_num_stateOperands(xtensa_isa isa, xtensa_opcode opc);
506 int xtensa_operand_encode(xtensa_isa isa, xtensa_opcode opc, int opnd,
509 int xtensa_operand_decode(xtensa_isa isa, xtensa_opcode opc, int opnd,
[all …]
/qemu/target/xtensa/
H A Dxtensa-isa.c662 xtensa_opcode opc; in xtensa_opcode_decode() local
670 if (opc != XTENSA_UNDEFINED) { in xtensa_opcode_decode()
671 return opc; in xtensa_opcode_decode()
689 CHECK_OPCODE(intisa, opc, -1); in xtensa_opcode_encode()
709 CHECK_OPCODE(intisa, opc, NULL); in xtensa_opcode_name()
710 return intisa->opcodes[opc].name; in xtensa_opcode_name()
809 CHECK_OPCODE(intisa, opc, NULL); in xtensa_opcode_funcUnit_use()
842 CHECK_OPCODE(intisa, opc, NULL); in get_operand()
856 intop = get_operand(intisa, opc, opnd); in xtensa_operand_name()
898 CHECK_OPCODE(intisa, opc, 0); in xtensa_operand_inout()
[all …]
/qemu/disas/
H A Dxtensa.c81 xtensa_opcode opc; in print_insn_xtensa() local
88 opc = xtensa_opcode_decode(isa, fmt, slot, slotbuf); in print_insn_xtensa()
89 if (opc == XTENSA_UNDEFINED) { in print_insn_xtensa()
93 opnds = xtensa_opcode_num_operands(isa, opc); in print_insn_xtensa()
95 info->fprintf_func(info->stream, "%s", xtensa_opcode_name(isa, opc)); in print_insn_xtensa()
98 if (xtensa_operand_is_visible(isa, opc, opnd)) { in print_insn_xtensa()
103 xtensa_operand_get_field(isa, opc, opnd, fmt, slot, in print_insn_xtensa()
105 rc = xtensa_operand_decode(isa, opc, opnd, &v); in print_insn_xtensa()
108 } else if (xtensa_operand_is_register(isa, opc, opnd)) { in print_insn_xtensa()
113 } else if (xtensa_operand_is_PCrelative(isa, opc, opnd)) { in print_insn_xtensa()
[all …]
H A Dhppa.c2332 int opc = GET_FIELD (insn, 0, 5); in print_insn_hppa() local
2334 if (opc == 0x16 || opc == 0x1e) in print_insn_hppa()
2348 int opc = GET_FIELD (insn, 0, 5); in print_insn_hppa() local
2350 if (opc == 0x13 || opc == 0x1b) in print_insn_hppa()
2357 else if (opc == 0x17 || opc == 0x1f) in print_insn_hppa()
/qemu/tcg/
H A Dtcg-op-vec.c68 TCGOpcode opc = *list; in tcg_can_emit_vecop_list() local
71 switch (opc) { in tcg_can_emit_vecop_list()
100 switch (opc) { in tcg_can_emit_vecop_list()
145 TCGOp *op = tcg_emit_op(opc, 2); in vec_gen_2()
155 TCGOp *op = tcg_emit_op(opc, 3); in vec_gen_3()
166 TCGOp *op = tcg_emit_op(opc, 4); in vec_gen_4()
178 TCGOp *op = tcg_emit_op(opc, 6); in vec_gen_6()
378 tcg_assert_listed_vecop(opc); in do_op2()
457 tcg_assert_listed_vecop(opc); in do_shifti()
545 tcg_assert_listed_vecop(opc); in do_op3()
[all …]
H A Dtcg-op-ldst.c118 gen_ldst(opc, vl, vh, addr, oi); in gen_ldst_i64()
184 TCGOpcode opc; in tcg_gen_qemu_ld_i32_int() local
237 TCGOpcode opc; in tcg_gen_qemu_st_i32_int() local
295 TCGOpcode opc; in tcg_gen_qemu_ld_i64_int() local
326 gen_ldst_i64(opc, val, addr, oi); in tcg_gen_qemu_ld_i64_int()
362 TCGOpcode opc; in tcg_gen_qemu_st_i64_int() local
398 gen_ldst_i64(opc, val, addr, oi); in tcg_gen_qemu_st_i64_int()
510 TCGOpcode opc; in tcg_gen_qemu_ld_i128_int() local
626 TCGOpcode opc; in tcg_gen_qemu_st_i128_int() local
739 switch (opc & MO_SSIZE) { in tcg_gen_ext_i32()
[all …]
H A Doptimize.c407 op->opc = new_op; in tcg_opt_gen_mov()
1464 switch (op->opc) { in fold_bswap()
1746 switch (op->opc) { in fold_exts()
1791 switch (op->opc) { in fold_extu()
1899 op->opc = opc; in fold_movcond()
1902 op->opc = opc; in fold_movcond()
2474 switch (op->opc) { in fold_shift()
2571 switch (op->opc) { in fold_tcg_ld()
2632 switch (op->opc) { in fold_tcg_st()
2725 TCGOpcode opc = op->opc; in tcg_optimize() local
[all …]
H A Dtcg-op.c40 void NI tcg_gen_op1(TCGOpcode opc, TCGArg a1) in tcg_gen_op1() argument
42 TCGOp *op = tcg_emit_op(opc, 1); in tcg_gen_op1()
48 TCGOp *op = tcg_emit_op(opc, 2); in tcg_gen_op2()
55 TCGOp *op = tcg_emit_op(opc, 3); in tcg_gen_op3()
63 TCGOp *op = tcg_emit_op(opc, 4); in tcg_gen_op4()
73 TCGOp *op = tcg_emit_op(opc, 5); in tcg_gen_op5()
84 TCGOp *op = tcg_emit_op(opc, 6); in tcg_gen_op6()
105 tcg_gen_op1(opc, tcgv_i32_arg(a1)); in tcg_gen_op1_i32()
110 tcg_gen_op1(opc, tcgv_i64_arg(a1)); in tcg_gen_op1_i64()
113 static void DNI tcg_gen_op1i(TCGOpcode opc, TCGArg a1) in tcg_gen_op1i() argument
[all …]
H A Dtcg.c2569 c = op->opc; in tcg_dump_ops()
3172 switch (op->opc) { in tcg_op_remove()
3226 op->opc = opc; in tcg_op_alloc()
3620 TCGOpcode opc = op->opc; in liveness_pass_1() local
3623 switch (opc) { in liveness_pass_1()
3768 op->opc = opc = opc_new; in liveness_pass_1()
3806 op->opc = opc = opc_new; in liveness_pass_1()
3811 op->opc = opc = opc_new2; in liveness_pass_1()
3969 TCGOpcode opc = op->opc; in liveness_pass_2() local
4057 if (opc == INDEX_op_mov_i32 || opc == INDEX_op_mov_i64) { in liveness_pass_2()
[all …]
/qemu/target/arm/tcg/
H A Dtranslate-a32.h100 TCGv_i32 a32, int index, MemOp opc);
102 TCGv_i32 a32, int index, MemOp opc);
104 TCGv_i32 a32, int index, MemOp opc);
106 TCGv_i32 a32, int index, MemOp opc);
108 int index, MemOp opc);
110 int index, MemOp opc);
112 int index, MemOp opc);
114 int index, MemOp opc);
H A Dtranslate.h600 if (s->align_mem && !(opc & MO_AMASK)) { in finalize_memop_atom()
601 opc |= MO_ALIGN; in finalize_memop_atom()
603 return opc | atom | s->be_data; in finalize_memop_atom()
613 static inline MemOp finalize_memop(DisasContext *s, MemOp opc) in finalize_memop() argument
616 return finalize_memop_atom(s, opc, atom); in finalize_memop()
627 static inline MemOp finalize_memop_pair(DisasContext *s, MemOp opc) in finalize_memop_pair() argument
630 return finalize_memop_atom(s, opc, atom); in finalize_memop_pair()
640 static inline MemOp finalize_memop_asimd(DisasContext *s, MemOp opc) in finalize_memop_asimd() argument
651 if ((opc & MO_SIZE) == MO_128) { in finalize_memop_asimd()
652 return finalize_memop_atom(s, opc, MO_ATOM_IFALIGN_PAIR); in finalize_memop_asimd()
[all …]
H A Dvfp.decode231 # We assemble bits 18 (op), 16 (u) and 7 (sx) into a single opc field
235 vd=%vd_sp imm=%vm_sp opc=%vcvt_fix_op
237 vd=%vd_sp imm=%vm_sp opc=%vcvt_fix_op
239 vd=%vd_dp imm=%vm_sp opc=%vcvt_fix_op
/qemu/tcg/tci/
H A Dtcg-target.c.inc698 static void tcg_out_op(TCGContext *s, TCGOpcode opc,
704 switch (opc) {
706 tcg_out_op_r(s, opc, args[0]);
710 tcg_out_op_l(s, opc, arg_label(args[0]));
736 tcg_out_ldst(s, opc, args[0], args[1], args[2]);
761 tcg_out_op_rrr(s, opc, args[0], args[1], args[2]);
790 tcg_out_op_rrrc(s, (opc == INDEX_op_brcond_i32
801 tcg_out_op_rr(s, opc, args[0], args[1]);
814 tcg_out_op_rr(s, opc, args[0], args[1]);
860 tcg_out_op_rrrrr(s, opc, args[0], args[1],
[all …]
/qemu/tcg/arm/
H A Dtcg-target.c.inc835 opc = ARITH_MOV;
838 opc = ARITH_MVN;
885 opc = opinv;
904 opc = opneg;
1549 switch (opc & MO_SSIZE) {
1667 switch (opc & MO_SIZE) {
1809 switch (opc) {
2422 opc = ARITH_SUB;
2618 switch (opc) {
2797 switch (opc) {
[all …]
/qemu/tcg/riscv/
H A Dtcg-target.c.inc387 tcg_out32(s, encode_r(opc, rd, rs1, rs2));
411 tcg_out32(s, encode_u(opc, rd, imm));
417 tcg_out32(s, encode_uj(opc, rd, imm));
677 switch (opc) {
1194 MemOp opc = get_memop(l->oi);
1212 MemOp opc = get_memop(l->oi);
1242 MemOp opc = get_memop(oi);
1250 unsigned s_bits = opc & MO_SIZE;
1363 switch (opc & (MO_SSIZE)) {
1415 switch (opc & (MO_SSIZE)) {
[all …]
/qemu/tcg/i386/
H A Dtcg-target.c.inc538 if (opc & P_GS) {
579 tcg_out8(s, opc);
600 tcg_out8(s, opc);
605 #define tcg_out_opc(s, opc, r, rm, x) (tcg_out_opc)(s, opc)
619 if (opc & P_GS) {
663 tcg_out8(s, opc);
707 tcg_out8(s, opc);
2586 switch (opc) {
3141 switch (opc) {
3668 switch (opc) {
[all …]
/qemu/tcg/mips/
H A Dtcg-target.c.inc373 inst = opc;
388 inst = opc;
403 inst = opc;
416 opc = oph;
420 opc = opm;
442 inst = opc;
479 inst = opc;
799 MIPSInsn opc = OPC_LD;
801 opc = OPC_LW;
811 opc = OPC_SW;
[all …]
/qemu/hw/net/
H A Detraxfs_eth.c163 unsigned int opc; member
233 bus->opc = 0; in mdio_cycle()
240 bus->opc <<= 1; in mdio_cycle()
241 bus->opc |= bus->mdio & 1; in mdio_cycle()
276 if (bus->opc == 2) { in mdio_cycle()
593 s->mdio_bus.opc = 0; in etraxfs_eth_reset()
/qemu/tcg/ppc/
H A Dtcg-target.c.inc363 #define OPCD(opc) ((opc)<<26)
364 #define XO19(opc) (OPCD(19)|((opc)<<1))
365 #define MD30(opc) (OPCD(30)|((opc)<<2))
366 #define MDS30(opc) (OPCD(30)|((opc)<<1))
367 #define XO31(opc) (OPCD(31)|((opc)<<1))
368 #define XO58(opc) (OPCD(58)|(opc))
369 #define XO62(opc) (OPCD(62)|(opc))
370 #define VX4(opc) (OPCD(4)|(opc))
2950 switch (opc) {
3543 switch (opc) {
[all …]
/qemu/tcg/loongarch64/
H A Dtcg-insn-defs.c.inc831 encode_d_slot(LoongArchInsn opc, uint32_t d)
833 return opc | d;
839 return opc | d | j << 5;
845 return opc | d | j << 5 | k << 10;
872 return opc | d | k << 10;
888 return encode_dj_slots(opc, d, j);
897 return encode_djk_slots(opc, d, j, k);
924 return encode_djk_slots(opc, d, j, uk12);
933 return encode_djk_slots(opc, d, j, uk5);
953 return encode_djk_slots(opc, d, j, uk6);
[all …]
H A Dtcg-target.c.inc792 switch (opc) {
921 MemOp opc = get_memop(l->oi);
936 MemOp opc = get_memop(l->oi);
974 MemOp opc = get_memop(oi);
981 unsigned s_bits = opc & MO_SIZE;
1066 tcg_debug_assert((opc & MO_BSWAP) == 0);
1068 switch (opc & MO_SSIZE) {
1120 switch (opc & MO_SIZE) {
1268 switch (opc) {
1890 switch (opc) {
[all …]
/qemu/target/mips/tcg/
H A Dtranslate.c2073 switch (opc) { in gen_ld()
2194 switch (opc) { in gen_st()
2280 switch (opc) { in gen_flt_ldst()
2347 if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) { in gen_arith_imm()
2354 switch (opc) { in gen_arith_imm()
2428 switch (opc) { in gen_logic_imm()
2478 switch (opc) { in gen_slt_imm()
2502 switch (opc) { in gen_shift_imm()
2566 if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB in gen_arith()
2567 && opc != OPC_DADD && opc != OPC_DSUB) { in gen_arith()
[all …]
H A Dnanomips_translate.c.inc1119 switch (opc) {
1164 switch (opc) {
1517 switch (opc) {
1551 switch (opc) {
1669 switch (opc) {
1788 switch (opc) {
2014 switch (opc) {
2149 switch (opc) {
2312 switch (opc) {
2439 switch (opc) {
[all …]
/qemu/hw/nvme/
H A Dnvme.h436 static inline const char *nvme_adm_opc_str(uint8_t opc) in nvme_adm_opc_str() argument
438 switch (opc) { in nvme_adm_opc_str()
459 static inline const char *nvme_io_opc_str(uint8_t opc) in nvme_io_opc_str() argument
461 switch (opc) { in nvme_io_opc_str()
/qemu/tcg/s390x/
H A Dtcg-target.c.inc1611 S390Opcode opc;
1631 opc = RIEc_CLIJ;
1634 opc = RIEc_CIJ;
1639 opc = RIEc_CLGIJ;
1642 opc = RIEc_CGIJ;
1853 MemOp opc = get_memop(oi);
1854 MemOp s_bits = opc & MO_SIZE;
2108 switch (opc) {
2852 switch (opc) {
2996 switch (opc) {
[all …]

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