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Searched refs:opcode (Results 1 – 25 of 154) sorted by relevance

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/qemu/linux-user/arm/nwfpe/
H A Dfpopcode.h204 #define getOffset(opcode) (opcode & MASK_OFFSET) argument
212 #define LDF_OP(opcode) (LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 1)) argument
213 #define LFM_OP(opcode) (LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 2)) argument
214 #define STF_OP(opcode) (STORE_OP(opcode) && (getCoprocessorNumber(opcode) == 1)) argument
215 #define SFM_OP(opcode) (STORE_OP(opcode) && (getCoprocessorNumber(opcode) == 2)) argument
222 #define LOAD(opcode) ((opcode & BIT_LOAD) != 0) argument
223 #define STORE(opcode) ((opcode & BIT_LOAD) == 0) argument
348 #define getCondition(opcode) (opcode >> 28) argument
357 #define getFn(opcode) ((opcode & MASK_Fn) >> 16) argument
360 #define getFm(opcode) (opcode & MASK_Fm) argument
[all …]
H A Dfpa11_cpdt.c231 if (BIT_UP_SET(opcode)) in PerformLDF()
267 if (BIT_UP_SET(opcode)) in PerformSTF()
300 if (BIT_UP_SET(opcode)) in PerformLFM()
307 Fd = getFd(opcode); in PerformLFM()
333 if (BIT_UP_SET(opcode)) in PerformSFM()
340 Fd = getFd(opcode); in PerformSFM()
359 if (LDF_OP(opcode)) in EmulateCPDT()
361 nRc = PerformLDF(opcode); in EmulateCPDT()
363 else if (LFM_OP(opcode)) in EmulateCPDT()
367 else if (STF_OP(opcode)) in EmulateCPDT()
[all …]
H A Dfpa11_cprt.c42 if (opcode & 0x800000) in EmulateCPRT()
48 return PerformComparison(opcode); in EmulateCPRT()
52 switch ((opcode & 0x700000) >> 20) in EmulateCPRT()
77 SetRoundingMode(opcode); in PerformFLT()
115 unsigned int Fn = getFm(opcode); in PerformFIX()
117 SetRoundingMode(opcode); in PerformFIX()
123 writeRegister(getRd(opcode), in PerformFIX()
131 writeRegister(getRd(opcode), in PerformFIX()
191 Fn = getFn(opcode); in PerformComparison()
192 Fm = getFm(opcode); in PerformComparison()
[all …]
H A Dfpa11.c147 cp = (opcode >> 8) & 0xf; in EmulateAll()
157 opcode, qregs[ARM_REG_PC]); in EmulateAll()
171 if (TEST_OPCODE(opcode,MASK_CPRT)) in EmulateAll()
177 nRc = EmulateCPRT(opcode); in EmulateAll()
184 nRc = EmulateCPDO(opcode); in EmulateAll()
191 nRc = EmulateCPDT(opcode); in EmulateAll()
213 switch ((opcode >> 24) & 0xf)
217 if ((opcode >> 20) & 0x1)
238 if (opcode & 0x10)
239 return EmulateCPDO(opcode);
[all …]
H A Dfpa11_cpdo.c25 unsigned int EmulateCPDO(const unsigned int opcode) in EmulateCPDO() argument
34 nDest = getDestinationSize(opcode); in EmulateCPDO()
37 SetRoundingMode(opcode); in EmulateCPDO()
44 if (MONADIC_INSTRUCTION(opcode)) in EmulateCPDO()
47 nType = fpa11->fType[getFn(opcode)]; in EmulateCPDO()
49 if (!CONSTANT_FM(opcode)) in EmulateCPDO()
51 register unsigned int Fm = getFm(opcode); in EmulateCPDO()
60 case typeSingle : nRc = SingleCPDO(opcode); break; in EmulateCPDO()
61 case typeDouble : nRc = DoubleCPDO(opcode); break; in EmulateCPDO()
62 case typeExtended : nRc = ExtendedCPDO(opcode); break; in EmulateCPDO()
[all …]
/qemu/target/hexagon/
H A Diclass.c35 if (GET_ATTRIB(opcode, A_ICOP)) { in find_iclass_slots()
45 } else if (GET_ATTRIB(opcode, A_COF) && in find_iclass_slots()
46 GET_ATTRIB(opcode, A_INDIRECT) && in find_iclass_slots()
47 !GET_ATTRIB(opcode, A_MEMLIKE) && in find_iclass_slots()
52 } else if ((opcode == J2_trap0) || in find_iclass_slots()
53 (opcode == Y2_isync) || in find_iclass_slots()
54 (opcode == J2_pause)) { in find_iclass_slots()
56 } else if (opcode == J4_hintjumpr) { in find_iclass_slots()
62 } else if (GET_ATTRIB(opcode, A_SUBINSN)) { in find_iclass_slots()
64 } else if (GET_ATTRIB(opcode, A_CALL)) { in find_iclass_slots()
[all …]
H A Ddecode.c193 if ((GET_ATTRIB(opcode, A_JUMP)) || in decode_opcode_can_jump()
195 (opcode == J2_trap0) || in decode_opcode_can_jump()
196 (opcode == J2_pause)) { in decode_opcode_can_jump()
198 if (opcode == J4_hintjumpr) { in decode_opcode_can_jump()
218 uint16_t opcode; in decode_set_insn_attr_fields() local
226 opcode = pkt->insn[i].opcode; in decode_set_insn_attr_fields()
297 int opcode = packet->insn[i].opcode; in decode_shuffle_for_execution() local
326 int opcode = packet->insn[i].opcode; in decode_shuffle_for_execution() local
520 insn->opcode = J2_endloop01; in decode_add_endloop_insn()
523 insn->opcode = J2_endloop1; in decode_add_endloop_insn()
[all …]
H A Dprintinsn.c41 switch (insn->opcode) { in snprintinsn()
66 if (pkt->insn[i].opcode == J2_endloop0) { in snprint_a_pkt_disas()
70 if (pkt->insn[i].opcode == J2_endloop1) { in snprint_a_pkt_disas()
74 if (pkt->insn[i].opcode == J2_endloop01) { in snprint_a_pkt_disas()
93 if (GET_ATTRIB(pkt->insn[i].opcode, A_SUBINSN)) { in snprint_a_pkt_disas()
97 } else if (pkt->insn[i + 1].opcode != J2_endloop0 && in snprint_a_pkt_disas()
98 pkt->insn[i + 1].opcode != J2_endloop1 && in snprint_a_pkt_disas()
119 int slot, opcode; in snprint_a_pkt_debug() local
132 if (GET_ATTRIB(pkt->insn[i].opcode, A_SUBINSN)) { in snprint_a_pkt_debug()
139 opcode = pkt->insn[i].opcode; in snprint_a_pkt_debug()
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H A Dtranslate.c263 uint16_t opcode = pkt->insn[i].opcode; in need_slot_cancelled() local
278 uint16_t opcode = pkt->insn[i].opcode; in need_next_PC() local
279 if (GET_ATTRIB(opcode, A_CONDEXEC) && GET_ATTRIB(opcode, A_COF)) { in need_next_PC()
297 uint16_t opcode = ctx->insn->opcode; in mark_implicit_reg_write() local
298 if (GET_ATTRIB(opcode, attrib)) { in mark_implicit_reg_write()
308 (opcode == J2_endloop0 || in mark_implicit_reg_write()
309 opcode == J2_endloop1 || in mark_implicit_reg_write()
310 opcode == J2_endloop01)) { in mark_implicit_reg_write()
563 uint16_t opcode = ctx->insn->opcode; in mark_store_width() local
775 int opcode = pkt->insn[i].opcode; in pkt_has_hvx_store() local
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/qemu/target/hexagon/mmvec/
H A Ddecode_ext_mmvec.c34 uint16_t use_opcode = pkt->insn[i].opcode; in check_new_value()
132 uint16_t opcode = pkt->insn[i].opcode; in decode_shuffle_for_execution_vops() local
133 if ((GET_ATTRIB(opcode, A_LOAD) && in decode_shuffle_for_execution_vops()
134 GET_ATTRIB(opcode, A_CVI_NEW)) || in decode_shuffle_for_execution_vops()
135 GET_ATTRIB(opcode, A_CVI_TMP)) { in decode_shuffle_for_execution_vops()
147 uint16_t opcode = pkt->insn[i].opcode; in decode_shuffle_for_execution_vops() local
148 if (GET_ATTRIB(opcode, A_STORE) && in decode_shuffle_for_execution_vops()
149 GET_ATTRIB(opcode, A_CVI_NEW) && in decode_shuffle_for_execution_vops()
176 int opcode = insn->opcode; in check_for_vhist() local
177 if (GET_ATTRIB(opcode, A_CVI) && GET_ATTRIB(opcode, A_CVI_4SLOT)) { in check_for_vhist()
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/qemu/target/ppc/translate/
H A Dspe-impl.c.inc28 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
29 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
65 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
220 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
221 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
307 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
308 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
316 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
325 if (rD(ctx->opcode) == rA(ctx->opcode)) {
377 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
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H A Dfp-impl.c.inc292 get_fpr(t0, rA(ctx->opcode));
293 get_fpr(t1, rB(ctx->opcode));
312 get_fpr(t0, rA(ctx->opcode));
313 get_fpr(t1, rB(ctx->opcode));
472 bfa = crfS(ctx->opcode);
477 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)],
675 flm = FPFLM(ctx->opcode);
676 l = FPL(ctx->opcode);
677 w = FPW(ctx->opcode);
711 w = FPW(ctx->opcode);
[all …]
H A Dvsx-impl.c.inc112 if (xT(ctx->opcode) < 32) {
403 if (xS(ctx->opcode) < 32) {
423 if (xS(ctx->opcode) < 32) {
443 if (xS(ctx->opcode) < 32) {
465 if (xS(ctx->opcode) < 32) {
484 if (xS(ctx->opcode) < 32) {
503 if (xS(ctx->opcode) < 32) {
522 if (xT(ctx->opcode) < 32) {
535 if (!rA(ctx->opcode)) {
549 if (xT(ctx->opcode) < 32) {
[all …]
/qemu/target/mips/tcg/
H A Dmxu_translate.c4406 uint32_t opcode = extract32(ctx->opcode, 18, 3); in decode_opc_mxu__pool00() local
4436 uint32_t opcode = extract32(ctx->opcode, 0, 6); in decode_opc_mxu_s32madd_sub() local
4465 uint32_t opcode = extract32(ctx->opcode, 18, 3); in decode_opc_mxu__pool01() local
4498 uint32_t opcode = extract32(ctx->opcode, 18, 3); in decode_opc_mxu__pool02() local
4522 uint32_t opcode = extract32(ctx->opcode, 24, 2); in decode_opc_mxu__pool03() local
4541 uint32_t opcode = extract32(ctx->opcode, 10, 4); in decode_opc_mxu__pool04() local
4554 uint32_t opcode = extract32(ctx->opcode, 10, 4); in decode_opc_mxu__pool05() local
4566 uint32_t opcode = extract32(ctx->opcode, 10, 4); in decode_opc_mxu__pool06() local
4586 uint32_t opcode = extract32(ctx->opcode, 10, 4); in decode_opc_mxu__pool07() local
4607 uint32_t opcode = extract32(ctx->opcode, 10, 4); in decode_opc_mxu__pool08() local
[all …]
H A Dmips16e_translate.c.inc462 ctx->opcode = (ctx->opcode << 16) | extend;
463 op = (ctx->opcode >> 11) & 0x1f;
464 sa = (ctx->opcode >> 22) & 0x1f;
465 funct = (ctx->opcode >> 8) & 0x7;
496 switch (ctx->opcode & 0x3) {
524 imm = ctx->opcode & 0xf;
528 if ((ctx->opcode >> 4) & 0x1) {
663 op = (ctx->opcode >> 11) & 0x1f;
664 sa = (ctx->opcode >> 2) & 0x7;
669 op1 = offset = ctx->opcode & 0x1f;
[all …]
H A Dnanomips_translate.c.inc1474 extract32(ctx->opcode, 11, 5), extract32(ctx->opcode, 3, 1));
1480 extract32(ctx->opcode, 11, 5), extract32(ctx->opcode, 3, 1));
2730 rt = extract32(ctx->opcode, 21, 5);
2731 rs = extract32(ctx->opcode, 16, 5);
3580 ctx->opcode = (ctx->opcode << 16) | insn;
3638 switch (ctx->opcode & 0x07) {
3678 switch (ctx->opcode & 0x03) {
4567 switch (ctx->opcode & 1) {
4605 switch (ctx->opcode & 0x1) {
4674 switch ((extract32(ctx->opcode, 3, 1) << 1) | (ctx->opcode & 1)) {
[all …]
H A Dmicromips_translate.c.inc873 switch (ctx->opcode & 0xf) {
888 if ((ctx->opcode >> 4) & 1) {
910 int enc_rs = (ctx->opcode & 3) | ((ctx->opcode >> 1) & 4);
928 switch (ctx->opcode & 0x3f) {
1631 ctx->opcode = (ctx->opcode << 16) | insn;
1633 rt = (ctx->opcode >> 21) & 0x1f;
1634 rs = (ctx->opcode >> 16) & 0x1f;
1636 rr = (ctx->opcode >> 6) & 0x1f;
1637 imm = (int16_t) ctx->opcode;
1642 minor = ctx->opcode & 0x3f;
[all …]
/qemu/hw/ppc/
H A Dspapr_hcall.c1510 assert((opcode & 0x3) == 0); in spapr_register_hypercall()
1513 } else if (opcode >= SVM_HCALL_BASE && opcode <= SVM_HCALL_MAX) { in spapr_register_hypercall()
1515 assert((opcode & 0x3) == 0); in spapr_register_hypercall()
1519 assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); in spapr_register_hypercall()
1533 assert((opcode & 0x3) == 0); in spapr_unregister_hypercall()
1536 } else if (opcode >= SVM_HCALL_BASE && opcode <= SVM_HCALL_MAX) { in spapr_unregister_hypercall()
1538 assert((opcode & 0x3) == 0); in spapr_unregister_hypercall()
1542 assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); in spapr_unregister_hypercall()
1555 if ((opcode <= MAX_HCALL_OPCODE) in spapr_hypercall()
1556 && ((opcode & 0x3) == 0)) { in spapr_hypercall()
[all …]
/qemu/target/ppc/
H A Dinternal.h66 static inline uint32_t name(uint32_t opcode) \
68 return extract32(opcode, shift, nb); \
72 static inline int32_t name(uint32_t opcode) \
74 return sextract32(opcode, shift, nb); \
78 static inline uint32_t name(uint32_t opcode) \
128 static inline uint32_t SPR(uint32_t opcode) in SPR() argument
130 uint32_t sprn = _SPR(opcode); in SPR()
185 static inline target_ulong LI(uint32_t opcode) in LI() argument
187 return (opcode >> 0) & 0x03FFFFFC; in LI()
190 static inline uint32_t BD(uint32_t opcode) in BD() argument
[all …]
H A Dtranslate.c171 uint32_t opcode; member
2296 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); in gen_slw()
2306 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); in gen_sraw()
2389 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); in gen_srad()
2512 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); in gen_addr_reg_index()
3857 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); in gen_mcrf()
5410 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); in gen_dlmzb()
5751 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); in gen_brd()
5757 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); in gen_brw()
5758 tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); in gen_brw()
[all …]
/qemu/hw/dma/
H A Dpl330.c308 uint8_t opcode; member
708 ns = !!(opcode & 2); in pl330_dmago()
736 uint8_t bs = opcode & 3; in pl330_dmald()
786 uint8_t lc = (opcode & 2) >> 1; in pl330_dmalp()
814 uint8_t bs = opcode & 3; in pl330_dmalpend()
914 uint8_t bs = opcode & 3; in pl330_dmast()
1018 uint8_t bs = opcode & 3; in pl330_dmawfp()
1110 uint8_t opcode; in pl330_fetch_insn() local
1116 if ((opcode & insn_desc[i].opmask) == insn_desc[i].opcode) { in pl330_fetch_insn()
1303 uint8_t opcode; in pl330_debug_exec() local
[all …]
/qemu/disas/
H A Dsparc.c1246 #define br(opcode, mask, lose, flags) \ argument
1265 #define tr(opcode, mask, lose, flags) \ argument
1422 movicc (opcode, cond, flags) /* v9 */
1845 #define SLCBCC2(opcode, mask, lose) \ argument
1848 #define SLCBCC(opcode, mask) \ argument
2270 const sparc_opcode *opcode; member
2414 const sparc_opcode *opcode = op->opcode; in is_delayed_branch() local
2416 if ((opcode->match & insn) == opcode->match in is_delayed_branch()
2633 h->opcode = opcode_table[i]; in build_hash_table()
2727 const sparc_opcode *opcode = op->opcode; in print_insn_sparc() local
[all …]
/qemu/target/tricore/
H A Dtranslate.c75 uint32_t opcode; member
3405 r1 = MASK_OP_SLR_D(ctx->opcode); in decode_slr_opc()
4958 r2 = MASK_OP_RC_D(ctx->opcode); in decode_rc_logical_shift()
5033 r2 = MASK_OP_RC_D(ctx->opcode); in decode_rc_accumulator()
5254 r2 = MASK_OP_RC_D(ctx->opcode); in decode_rc_mul()
5584 r3 = MASK_OP_RR_D(ctx->opcode); in decode_rr_accumulator()
5925 r3 = MASK_OP_RR_D(ctx->opcode); in decode_rr_logical_shift()
6001 r3 = MASK_OP_RR_D(ctx->opcode); in decode_rr_address()
6004 n = MASK_OP_RR_N(ctx->opcode); in decode_rr_address()
6099 r3 = MASK_OP_RR_D(ctx->opcode); in decode_rr_divide()
[all …]
/qemu/hw/ufs/
H A Dtrace-events11 ufs_exec_scsi_cmd(uint32_t slot, uint8_t lun, uint8_t opcode) "slot %"PRIu32", lun 0x%"PRIx8", opcode 0x%"PRIx8""
12 ufs_exec_query_cmd(uint32_t slot, uint8_t opcode) "slot %"PRIu32", opcode 0x%"PRIx8""
35 ufs_err_query_invalid_opcode(uint8_t opcode) "query request has invalid opcode. opcode: 0x%"PRIx8""
36 ufs_err_query_invalid_idn(uint8_t opcode, uint8_t idn) "query request has invalid idn. opcode: 0x%"PRIx8", idn 0x%"PRIx8""
37 ufs_err_query_invalid_index(uint8_t opcode, uint8_
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/qemu/hw/i386/
H A Dvapic.c82 uint8_t opcode; member
93 .opcode = 0xa1,
99 .opcode = 0xa3,
105 .opcode = 0x89,
112 .opcode = 0x8b,
119 .opcode = 0xff,
127 .opcode = 0xc7,
196 return opcode[0] == instr->opcode && in opcode_matches()
208 uint8_t opcode[2]; in evaluate_tpr_instruction() local
252 if (cpu_memory_rw_debug(cs, ip, opcode, sizeof(opcode), 0) < 0) { in evaluate_tpr_instruction()
[all …]

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