/qemu/tests/tcg/loongarch64/system/ |
H A D | boot.S | 39 ori t0, t2, 0x1e5 49 ori t0, t0, 0x1e0
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/qemu/tests/migration/ppc64/ |
H A D | a-b-kernel.S | 40 ori %r20,%r20,PPC_TEST_MEM_START@l 42 ori %r9,%r9,PPC_TEST_MEM_END@l
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/qemu/pc-bios/vof/ |
H A D | entry.S | 3 ori rn,rn,name##@l
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/qemu/target/microblaze/ |
H A D | insns.decode | 201 ori 101000 ..... ..... ................ @typeb
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H A D | translate.c | 519 DO_TYPEBI(ori, false, tcg_gen_ori_i32) in DO_TYPEA_CFG()
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/qemu/target/riscv/ |
H A D | insn32.decode | 140 # cbo.prefetch_{i,r,m} instructions are ori with rd=x0 and not decoded. 141 ori ............ ..... 110 ..... 0010011 @i
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/qemu/target/openrisc/ |
H A D | disas.c | 107 INSN(ori, "r%d, r%d, %d", a->d, a->a, a->k)
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/qemu/target/loongarch/tcg/insn_trans/ |
H A D | trans_arith.c.inc | 303 TRANS(ori, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_ori_tl)
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/qemu/disas/ |
H A D | microblaze.c | 107 bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni, enumerator 365 …_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, ori, logical_inst },
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/qemu/target/s390x/tcg/ |
H A D | insn-data.h.inc | 740 D(0xc00c, OIHF, RIL_a, EI, r1_o, i2_32u, r1, 0, ori, 0, 0x2020) 741 D(0xc00d, OILF, RIL_a, EI, r1_o, i2_32u, r1, 0, ori, 0, 0x2000) 742 D(0xa508, OIHH, RI_a, Z, r1_o, i2_16u, r1, 0, ori, 0, 0x1030) 743 D(0xa509, OIHL, RI_a, Z, r1_o, i2_16u, r1, 0, ori, 0, 0x1020) 744 D(0xa50a, OILH, RI_a, Z, r1_o, i2_16u, r1, 0, ori, 0, 0x1010) 745 D(0xa50b, OILL, RI_a, Z, r1_o, i2_16u, r1, 0, ori, 0, 0x1000)
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H A D | translate_vx.c.inc | 3202 gen_gvec_fn_2i(ori, ES_32, v1, v2, 1ull << 31); 3221 gen_gvec_fn_2i(ori, ES_64, v1, v2, 1ull << 63);
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/qemu/tcg/loongarch64/ |
H A D | tcg-target.c.inc | 329 /* val fits in uimm12: ori rd, zero, val */ 339 /* High bits must be set; load with lu12i.w + optional ori. */ 388 /* Offset within 32 bits; load with pcalau12i + ori. */ 2182 * can express using andi/ori if ~constant satisfies
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H A D | tcg-insn-defs.c.inc | 1729 /* Emits the `ori d, j, uk12` instruction. */
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/qemu/target/loongarch/ |
H A D | insns.decode | 152 ori 0000 001110 ............ ..... ..... @rr_ui12
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H A D | disas.c | 529 INSN(ori, rr_i) in INSN()
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/qemu/target/riscv/insn_trans/ |
H A D | trans_rvv.c.inc | 1742 GEN_OPIVI_GVEC_TRANS(vor_vi, IMM_SX, vor_vx, ori)
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/qemu/tcg/ppc/ |
H A D | tcg-target.c.inc | 535 #define NOP ORI /* ori 0,0,0 */
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