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Searched refs:plic (Results 1 – 11 of 11) sorted by relevance

/qemu/hw/intc/
H A Dsifive_plic.c84 (plic->pending[i] & ~plic->claimed[i]) & in sifive_plic_claimed()
85 plic->enable[addrid * plic->bitfield_words + i]; in sifive_plic_claimed()
142 if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) { in sifive_plic_read()
152 plic->num_addrs * plic->enable_stride)) { in sifive_plic_read()
157 return plic->enable[addrid * plic->bitfield_words + wordid]; in sifive_plic_read()
160 plic->num_addrs * plic->context_stride)) { in sifive_plic_read()
193 if (((plic->num_priorities + 1) & plic->num_priorities) == 0) { in sifive_plic_write()
211 plic->num_addrs * plic->enable_stride)) { in sifive_plic_write()
216 plic->enable[addrid * plic->bitfield_words + wordid] = value; in sifive_plic_write()
223 plic->num_addrs * plic->context_stride)) { in sifive_plic_write()
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/qemu/hw/riscv/
H A Dopentitan.c177 qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M"); in lowrisc_ibex_soc_realize()
178 qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180); in lowrisc_ibex_soc_realize()
179 qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3); in lowrisc_ibex_soc_realize()
182 qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32); in lowrisc_ibex_soc_realize()
184 qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8); in lowrisc_ibex_soc_realize()
187 if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) { in lowrisc_ibex_soc_realize()
206 0, qdev_get_gpio_in(DEVICE(&s->plic), in lowrisc_ibex_soc_realize()
209 1, qdev_get_gpio_in(DEVICE(&s->plic), in lowrisc_ibex_soc_realize()
212 2, qdev_get_gpio_in(DEVICE(&s->plic), in lowrisc_ibex_soc_realize()
215 3, qdev_get_gpio_in(DEVICE(&s->plic), in lowrisc_ibex_soc_realize()
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H A Dmicrochip_pfsoc.c281 s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base, in microchip_pfsoc_soc_realize()
300 qdev_get_gpio_in(DEVICE(s->plic), in microchip_pfsoc_soc_realize()
309 qdev_get_gpio_in(DEVICE(s->plic), in microchip_pfsoc_soc_realize()
347 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ), in microchip_pfsoc_soc_realize()
351 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ), in microchip_pfsoc_soc_realize()
355 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ), in microchip_pfsoc_soc_realize()
359 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ), in microchip_pfsoc_soc_realize()
363 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ), in microchip_pfsoc_soc_realize()
422 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ)); in microchip_pfsoc_soc_realize()
430 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ)); in microchip_pfsoc_soc_realize()
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H A Dsifive_e.c211 s->plic = sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base, in sifive_e_soc_realize()
255 qdev_get_gpio_in(DEVICE(s->plic), in sifive_e_soc_realize()
259 qdev_get_gpio_in(DEVICE(s->plic), in sifive_e_soc_realize()
263 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ)); in sifive_e_soc_realize()
269 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ)); in sifive_e_soc_realize()
H A Dsifive_u.c830 s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base, in sifive_u_soc_realize()
843 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); in sifive_u_soc_realize()
845 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); in sifive_u_soc_realize()
871 qdev_get_gpio_in(DEVICE(s->plic), in sifive_u_soc_realize()
882 qdev_get_gpio_in(DEVICE(s->plic), in sifive_u_soc_realize()
900 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ)); in sifive_u_soc_realize()
913 qdev_get_gpio_in(DEVICE(s->plic), in sifive_u_soc_realize()
931 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IRQ)); in sifive_u_soc_realize()
936 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ)); in sifive_u_soc_realize()
H A Dshakti_c.c112 sss->plic = sifive_plic_create(shakti_c_memmap[SHAKTI_C_PLIC].base, in type_init()
/qemu/include/hw/riscv/
H A Dshakti_c.h36 DeviceState *plic; member
H A Dsifive_e.h38 DeviceState *plic; member
H A Dopentitan.h45 SiFivePLICState plic; member
H A Dsifive_u.h47 DeviceState *plic; member
H A Dmicrochip_pfsoc.h45 DeviceState *plic; member