| /qemu/hw/misc/ |
| H A D | imx7_ccm.c | 27 memset(s->pmu, 0, sizeof(s->pmu)); in imx7_analog_reset()
189 memory_region_init_io(&s->mmio.pmu, in imx7_analog_init()
192 s->pmu, in imx7_analog_init()
194 sizeof(s->pmu)); in imx7_analog_init()
197 0x200, &s->mmio.pmu); in imx7_analog_init()
291 VMSTATE_UINT32_ARRAY(pmu, IMX7AnalogState, PMU_MAX),
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| /qemu/hw/microblaze/ |
| H A D | xlnx-zynqmp-pmu.c | 152 XlnxZynqMPPMUSoCState *pmu = g_new0(XlnxZynqMPPMUSoCState, 1); in type_init() local
170 object_initialize_child(OBJECT(machine), "pmu", pmu, in type_init()
172 qdev_realize(DEVICE(pmu), NULL, &error_fatal); in type_init()
175 microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR, in type_init()
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| H A D | meson.build | 5 microblaze_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-zynqmp-pmu.c'))
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| /qemu/include/hw/misc/ |
| H A D | imx7_ccm.h | 133 MemoryRegion pmu; member
137 uint32_t pmu[PMU_MAX]; member
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| /qemu/hw/misc/macio/ |
| H A D | macio.c | 320 object_initialize_child(OBJECT(s), "pmu", &s->pmu, TYPE_VIA_PMU); in macio_newworld_realize()
321 object_property_set_link(OBJECT(&s->pmu), "gpio", OBJECT(sbd), in macio_newworld_realize()
323 qdev_prop_set_bit(DEVICE(&s->pmu), "has-adb", ns->has_adb); in macio_newworld_realize()
324 if (!qdev_realize(DEVICE(&s->pmu), BUS(&s->macio_bus), errp)) { in macio_newworld_realize()
327 sbd = SYS_BUS_DEVICE(&s->pmu); in macio_newworld_realize()
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| H A D | meson.build | 6 macio_ss.add(when: 'CONFIG_MAC_PMU', if_true: files('pmu.c'))
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| H A D | trace-events | 23 # pmu.c
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| /qemu/docs/system/arm/ |
| H A D | cpu-features.rst | 13 a PMU, then the ``-cpu`` parameter should contain ``pmu=off`` on the QEMU
14 command line, i.e. ``-cpu cortex-a15,pmu=off``.
47 "sve1664": true, "pmu": true, "sve1792": true, "sve1920": true,
54 We see that the ``max`` CPU type has the ``pmu``, ``aarch64``, ``sve``, and many
67 "sve1664": true, "pmu": false, "sve1792": true, "sve1920": true,
74 We see it worked, as ``pmu`` is now ``false``.
93 "sve1664": false, "pmu": true, "sve1792": false, "sve1920": false,
105 {"return": {"model": {"name": "cortex-a15", "props": {"pmu": true}}}}
107 Only the ``pmu`` CPU feature is available.
158 $ qemu-system-aarch64 -M virt -cpu max,pmu=off,sve=on,sve128=on,sve256=on
[all …]
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| /qemu/include/hw/misc/macio/ |
| H A D | macio.h | 109 PMUState pmu; member
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| /qemu/target/riscv/ |
| H A D | meson.build | 35 'pmu.c',
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| /qemu/target/ppc/ |
| H A D | meson.build | 19 'power8-pmu.c',
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| /qemu/hw/intc/ |
| H A D | meson.build | 33 system_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-intc.c'))
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| /qemu/docs/about/ |
| H A D | deprecated.rst | 417 ``pmu-num=n`` on RISC-V CPUs (since 8.2)
421 by a ``pmu-mask`` property. If set of counters is continuous then the mask can
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| /qemu/hw/arm/ |
| H A D | virt.c | 2008 bool aarch64, pmu, steal_time; in virt_cpu_post_init() local
2012 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); in virt_cpu_post_init()
2040 if (pmu) { in virt_cpu_post_init()
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| /qemu/tests/data/qobject/ |
| H A D | qdict.txt | 829 ams-pmu.c: 4469
1640 bast-pmu.h: 1140
2588 cell-pmu.h: 4133
|