Searched refs:tcg_gen_concat_tl_i64 (Results 1 – 12 of 12) sorted by relevance
/qemu/include/tcg/ |
H A D | tcg-op.h | 229 #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64 macro 347 #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
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/qemu/target/riscv/insn_trans/ |
H A D | trans_rvk.c.inc | 203 tcg_gen_concat_tl_i64(t0, src1, src2); 258 tcg_gen_concat_tl_i64(t0, src1, src2);
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H A D | trans_rvzacas.c.inc | 55 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]);
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H A D | trans_rvzfa.c.inc | 427 tcg_gen_concat_tl_i64(cpu_fpr[a->rd], src1, src2);
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/qemu/target/loongarch/tcg/insn_trans/ |
H A D | trans_bit.c.inc | 21 tcg_gen_concat_tl_i64(dest, src1, src2);
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/qemu/target/i386/tcg/ |
H A D | translate.c | 1518 tcg_gen_concat_tl_i64(s->T0, s->T0, s->T1); in gen_shiftd_rm_T1() 1522 tcg_gen_concat_tl_i64(s->T0, s->T1, s->T0); in gen_shiftd_rm_T1() 2416 tcg_gen_concat_tl_i64(cmp, cpu_regs[R_EAX], cpu_regs[R_EDX]); in gen_cmpxchg8b() 2417 tcg_gen_concat_tl_i64(val, cpu_regs[R_EBX], cpu_regs[R_ECX]); in gen_cmpxchg8b() 3718 tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX], in disas_insn_old() 3886 tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX], in disas_insn_old() 4325 tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX], in disas_insn_old() 4337 tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX], in disas_insn_old() 4363 tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX], in disas_insn_old()
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/qemu/target/mips/tcg/ |
H A D | nanomips_translate.c.inc | 1035 tcg_gen_concat_tl_i64(tval, tmp2, tmp1); 1037 tcg_gen_concat_tl_i64(tval, tmp1, tmp2); 1823 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); 1879 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); 1942 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); 1985 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
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H A D | translate.c | 3381 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); in gen_muldiv() 3397 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); in gen_muldiv() 3411 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); in gen_muldiv() 3427 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); in gen_muldiv() 3522 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); in gen_mul_txx9() 3544 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); in gen_mul_txx9() 5005 tcg_gen_concat_tl_i64(t2, t1, t0); in gen_align_bits()
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H A D | mxu_translate.c | 4382 tcg_gen_concat_tl_i64(t3, t1, t0); in gen_mxu_s32madd_sub()
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/qemu/target/sparc/ |
H A D | translate.c | 2288 tcg_gen_concat_tl_i64(t64, lo, hi); in gen_stda_asi() 2290 tcg_gen_concat_tl_i64(t64, hi, lo); in gen_stda_asi() 2308 tcg_gen_concat_tl_i64(t8, lo, hi); in gen_stda_asi() 2327 tcg_gen_concat_tl_i64(t64, lo, hi); in gen_stda_asi() 2329 tcg_gen_concat_tl_i64(t64, hi, lo); in gen_stda_asi() 3779 tcg_gen_concat_tl_i64(t1, gen_load_gpr(dc, a->rs1), cpu_y); in trans_UDIV()
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/qemu/target/ppc/translate/ |
H A D | spe-impl.c.inc | 21 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], 34 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
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/qemu/target/riscv/ |
H A D | translate.c | 472 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); in get_fpr_d()
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