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Searched refs:tcg_gen_sub_i32 (Results 1 – 20 of 20) sorted by relevance

/qemu/include/tcg/
H A Dtcg-op-gvec.h38 #define tcg_gen_vec_sub32_tl tcg_gen_sub_i32
H A Dtcg-op.h299 #define tcg_gen_sub_tl tcg_gen_sub_i32
H A Dtcg-op-common.h172 void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
/qemu/target/m68k/
H A Dtranslate.c548 tcg_gen_sub_i32(t0, QREG_CC_N, QREG_CC_V); in gen_flush_flags()
1203 tcg_gen_sub_i32(tmp, QREG_CC_N, QREG_CC_V); in gen_cc_cond()
1651 tcg_gen_sub_i32(dest, t1, dest); in bcd_add()
1673 tcg_gen_sub_i32(t1, t1, QREG_CC_X); in bcd_sub()
1703 tcg_gen_sub_i32(dest, t1, t0); in bcd_sub()
1834 tcg_gen_sub_i32(dest, tmp, src); in DISAS_INSN()
2005 tcg_gen_sub_i32(addr, addr, incr); in DISAS_INSN()
2277 tcg_gen_sub_i32(dest, src1, im); in DISAS_INSN()
2953 tcg_gen_sub_i32(dest, dest, val); in DISAS_INSN()
2960 tcg_gen_sub_i32(dest, dest, val); in DISAS_INSN()
[all …]
/qemu/tcg/
H A Dtcg-op.c359 void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) in tcg_gen_sub_i32() function
369 tcg_gen_sub_i32(ret, tcg_constant_i32(arg1), arg2); in tcg_gen_subfi_i32()
601 tcg_gen_sub_i32(ret, arg1, t0); in tcg_gen_rem_i32()
635 tcg_gen_sub_i32(ret, arg1, t0); in tcg_gen_remu_i32()
1219 tcg_gen_sub_i32(rh, t1, t2); in tcg_gen_muls2_i32()
1220 tcg_gen_sub_i32(rh, rh, t3); in tcg_gen_muls2_i32()
1248 tcg_gen_sub_i32(rh, t1, t2); in tcg_gen_mulsu2_i32()
1413 tcg_gen_sub_i32(ret, ret, t); in tcg_gen_abs_i32()
H A Dtcg-op-gvec.c2005 { .fni4 = tcg_gen_sub_i32, in tcg_gen_gvec_subs()
2058 tcg_gen_sub_i32(d, t1, t2); in tcg_gen_vec_sub8_i32()
2079 tcg_gen_sub_i32(t2, a, b); in tcg_gen_vec_sub16_i32()
2080 tcg_gen_sub_i32(t1, a, t1); in tcg_gen_vec_sub16_i32()
2115 { .fni4 = tcg_gen_sub_i32, in tcg_gen_gvec_sub()
2296 tcg_gen_sub_i32(d, a, b); in tcg_gen_ussub_i32()
/qemu/target/microblaze/
H A Dtranslate.c421 tcg_gen_sub_i32(out, inb, ina); in DO_TYPEA0_CFG()
430 tcg_gen_sub_i32(out, inb, ina); in gen_cmpu()
539 tcg_gen_sub_i32(out, inb, ina); in DO_TYPEA_CFG()
556 tcg_gen_sub_i32(out, inb, ina); in gen_rsubk()
/qemu/accel/tcg/
H A Dtranslator.c60 tcg_gen_sub_i32(count, count, tcg_constant_i32(0)); in gen_tb_start()
/qemu/target/arm/tcg/
H A Dtranslate.c471 tcg_gen_sub_i32(dest, t0, t1); in gen_sub_carry()
518 tcg_gen_sub_i32(cpu_NF, t0, t1); in gen_sub_CC()
3728 tcg_gen_sub_i32(d, d, a); in gen_mls32_i32()
4281 tcg_gen_sub_i32(t, a, b); in gen_sabd_i32()
4282 tcg_gen_sub_i32(d, b, a); in gen_sabd_i32()
4338 tcg_gen_sub_i32(t, a, b); in gen_uabd_i32()
4339 tcg_gen_sub_i32(d, b, a); in gen_uabd_i32()
5225 tcg_gen_sub_i32(dst, b, a); in gen_rsb()
5842 tcg_gen_sub_i32(t1, t2, t1); in trans_MLS()
6522 tcg_gen_sub_i32(addr, addr, ofs); in op_addr_rr_pre()
[all …]
H A Dtranslate-neon.c2408 tcg_gen_sub_i32, in trans_VMLS_2sc()
H A Dtranslate-a64.c870 tcg_gen_sub_i32(cpu_NF, t0_32, t1_32); in gen_sub32_CC()
13156 { tcg_gen_add_i32, tcg_gen_sub_i32 }, in disas_simd_indexed()
H A Dtranslate-sve.c3422 { .fni4 = tcg_gen_sub_i32, in trans_SUBR_zzi()
/qemu/target/sh4/
H A Dtranslate.c920 tcg_gen_sub_i32(REG(B11_8), REG(B11_8), REG(B7_4)); in _decode_opc()
942 tcg_gen_sub_i32(result, Rn, Rm); in _decode_opc()
/qemu/target/rx/
H A Dtranslate.c1041 tcg_gen_sub_i32(cpu_psw_s, arg1, arg2); in rx_sub()
1317 tcg_gen_sub_i32(count, tcg_constant_i32(32), tmp); in trans_SHLL_rr()
/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_vec.c.inc705 tcg_gen_sub_i32(t, t1, t2);
788 tcg_gen_sub_i32(t, t1, t2);
1029 tcg_gen_sub_i32(t, t1, t2);
1112 tcg_gen_sub_i32(t, t1, t2);
2649 tcg_gen_sub_i32(t, t, t1);
/qemu/target/mips/tcg/
H A Dmxu_translate.c3470 tcg_gen_sub_i32(t2, t0, t1); in gen_mxu_d32add()
3483 tcg_gen_sub_i32(t2, t0, t1); in gen_mxu_d32add()
/qemu/target/ppc/translate/
H A Dspe-impl.c.inc226 tcg_gen_sub_i32(ret, arg2, arg1);
/qemu/target/xtensa/
H A Dtranslate.c305 tcg_gen_sub_i32(cpu_SR[SAR], tcg_constant_i32(32), dc->sar_m32); in gen_left_shift_sar()
2388 tcg_gen_sub_i32(arg[0].out, arg[1].in, arg[2].in); in translate_sub()
2396 tcg_gen_sub_i32(arg[0].out, tmp, arg[2].in); in translate_subx()
/qemu/target/sparc/
H A Dtranslate.c4605 TRANS(FPSUB32s, VIS1, do_fff, a, tcg_gen_sub_i32) in TRANS()
/qemu/target/riscv/insn_trans/
H A Dtrans_rvv.c.inc1307 tcg_gen_sub_i32(ret, arg2, arg1);