/qemu/target/arm/ |
H A D | machine.c | 55 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[0].d, ARMCPU, 0, 2), 56 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[1].d, ARMCPU, 0, 2), 57 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[2].d, ARMCPU, 0, 2), 58 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[3].d, ARMCPU, 0, 2), 59 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[4].d, ARMCPU, 0, 2), 60 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[5].d, ARMCPU, 0, 2), 61 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[6].d, ARMCPU, 0, 2), 62 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[7].d, ARMCPU, 0, 2), 63 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[8].d, ARMCPU, 0, 2), 64 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[9].d, ARMCPU, 0, 2), [all …]
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H A D | gdbstub64.c | 137 env->vfp.zregs[reg].d[vq * 2 + 1], in aarch64_gdb_get_sve_reg() 138 env->vfp.zregs[reg].d[vq * 2]); in aarch64_gdb_get_sve_reg() 187 env->vfp.zregs[reg].d[vq * 2 + 1] = *p++; in aarch64_gdb_set_sve_reg() 188 env->vfp.zregs[reg].d[vq * 2] = *p++; in aarch64_gdb_set_sve_reg()
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H A D | arch_dump.c | 208 r = sve_bswap64(tmp, &env->vfp.zregs[i].d[0], vq * 2); in aarch64_write_elf64_sve()
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H A D | cpu.c | 1331 i, env->vfp.zregs[i].d[1], in aarch64_cpu_dump_state() 1332 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); in aarch64_cpu_dump_state() 1339 env->vfp.zregs[i].d[j * 2 + 1], in aarch64_cpu_dump_state() 1340 env->vfp.zregs[i].d[j * 2 + 0], in aarch64_cpu_dump_state()
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H A D | cpu.h | 607 ARMVectorReg zregs[32]; member 3255 return &env->vfp.zregs[regno >> 1].d[regno & 1]; in aa32_vfp_dreg() 3264 return &env->vfp.zregs[regno].d[0]; in aa32_vfp_qreg() 3273 return &env->vfp.zregs[regno].d[0]; in aa64_vfp_qreg()
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H A D | kvm.c | 2024 r = sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * 2); in kvm_arch_put_sve() 2207 r = &env->vfp.zregs[n].d[0]; in kvm_arch_get_sve()
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H A D | helper.c | 7344 memset(env->vfp.zregs, 0, sizeof(env->vfp.zregs)); in arm_reset_sve_state() 12743 memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq)); in aarch64_sve_narrow_vq()
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/qemu/target/arm/hvf/ |
H A D | hvf.c | 358 { HV_SIMD_FP_REG_Q0, offsetof(CPUARMState, vfp.zregs[0]) }, 359 { HV_SIMD_FP_REG_Q1, offsetof(CPUARMState, vfp.zregs[1]) }, 360 { HV_SIMD_FP_REG_Q2, offsetof(CPUARMState, vfp.zregs[2]) }, 361 { HV_SIMD_FP_REG_Q3, offsetof(CPUARMState, vfp.zregs[3]) }, 362 { HV_SIMD_FP_REG_Q4, offsetof(CPUARMState, vfp.zregs[4]) }, 363 { HV_SIMD_FP_REG_Q5, offsetof(CPUARMState, vfp.zregs[5]) }, 364 { HV_SIMD_FP_REG_Q6, offsetof(CPUARMState, vfp.zregs[6]) }, 365 { HV_SIMD_FP_REG_Q7, offsetof(CPUARMState, vfp.zregs[7]) }, 366 { HV_SIMD_FP_REG_Q8, offsetof(CPUARMState, vfp.zregs[8]) }, 367 { HV_SIMD_FP_REG_Q9, offsetof(CPUARMState, vfp.zregs[9]) }, [all …]
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/qemu/target/arm/tcg/ |
H A D | translate-a64.h | 104 offs += offsetof(CPUARMState, vfp.zregs[regno]); in vec_reg_offset() 113 return offsetof(CPUARMState, vfp.zregs[regno]); in vec_full_reg_offset()
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H A D | sve_helper.c | 5669 memset(&env->vfp.zregs[(rd + i) & 31], 0, reg_max); in sve_ldN_r() 5725 memcpy(&env->vfp.zregs[(rd + i) & 31], &scratch[i], reg_max); in sve_ldN_r() 5733 memset(&env->vfp.zregs[(rd + i) & 31], 0, reg_max); in sve_ldN_r() 5746 host_fn(&env->vfp.zregs[(rd + i) & 31], reg_off, in sve_ldN_r() 5763 tlb_fn(env, &env->vfp.zregs[(rd + i) & 31], reg_off, in sve_ldN_r() 5779 host_fn(&env->vfp.zregs[(rd + i) & 31], reg_off, in sve_ldN_r() 5976 void *vd = &env->vfp.zregs[rd]; in sve_ldnfff1_r() 6334 tlb_fn(env, &env->vfp.zregs[(rd + i) & 31], reg_off, in DO_LDFF1_LDNF1_1() 6356 host_fn(&env->vfp.zregs[(rd + i) & 31], reg_off, in DO_LDFF1_LDNF1_1() 6373 tlb_fn(env, &env->vfp.zregs[(rd + i) & 31], reg_off, in DO_LDFF1_LDNF1_1() [all …]
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H A D | translate-mve.c | 53 return offsetof(CPUARMState, vfp.zregs[reg].d[0]); in mve_qreg_offset()
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H A D | translate.c | 1149 return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]); in neon_full_reg_offset()
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/qemu/linux-user/aarch64/ |
H A D | signal.c | 215 __put_user_e(env->vfp.zregs[i].d[j], z + j, le); in target_setup_sve_record() 349 __get_user_e(env->vfp.zregs[i].d[j], z + j, le); in target_restore_sve_record()
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