| /qemu/hw/pci-host/ |
| H A D | designware.c | 411 pci_set_word(dev->config + PCI_COMMAND, in designware_pcie_root_realize()
414 pci_config_set_interrupt_pin(dev->config, 1); in designware_pcie_root_realize()
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| H A D | trace-events | 4 bonito_spciconf_small_access(uint64_t addr, unsigned size) "PCI config address is smaller then 32-b…
34 unin_get_config_reg(uint32_t reg, uint32_t addr, uint32_t retval) "converted config space accessor …
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| H A D | Kconfig | 1 config PAM
9 config PPC4XX_PCI
13 config PPC440_PCIX
17 config RAVEN_PCI
26 config UNIN_PCI
40 config PCI_SABRE
80 config SH_PCI
84 config ARTICIA
89 config MV64361
94 config DINO
[all …]
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| /qemu/hw/misc/ |
| H A D | Kconfig | 1 config APPLESMC
5 config ARMSSE_CPUID
8 config ARMSSE_MHU
14 config ISA_DEBUG
28 config EDU
46 config PL310
52 config A9SCU
61 config MACIO
79 config IMX
146 config AUX
[all …]
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| H A D | bcm2835_property.c | 41 BCM2835FBConfig fbconfig = s->fbdev->config; in bcm2835_property_mbox_push()
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| /qemu/hw/net/ |
| H A D | trace-events | 234 …2_t int_cfg, uint32_t vec) "Clearing MSI-X pending bit for cause 0x%x, IVAR config 0x%x, vector %u"
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| H A D | tulip.c | 965 pci_conf = s->dev.config; in pci_tulip_realize()
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| /qemu/hw/pci-bridge/ |
| H A D | cxl_downstream.c | 51 uint8_t *reg = &dev->config[addr]; in cxl_dsp_dvsec_write_config()
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| /qemu/hw/isa/ |
| H A D | Kconfig | 1 config ISA_BUS
4 config APM
7 config I82378
16 config ISA_SUPERIO
26 config FDC37M81X
30 config PC87312
39 config PIIX
52 config VT82C686
66 config SMC37C669
70 config LPC_ICH9
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| H A D | lpc_ich9.c | 196 ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num], in ich9_lpc_pic_irq()
335 uint8_t sel = lpc->d.config[ICH9_LPC_ACPI_CTRL] & in ich9_lpc_sci_irq()
488 uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE); in ich9_lpc_pmbase_sci_update()
515 uint32_t rcba = pci_get_long(lpc->d.config + ICH9_LPC_RCBA); in ich9_lpc_rcba_update()
556 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); in ich9_lpc_config_write()
581 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); in ich9_lpc_reset()
585 pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i, in ich9_lpc_reset()
589 pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i, in ich9_lpc_reset()
594 pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT); in ich9_lpc_reset()
595 pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT); in ich9_lpc_reset()
[all …]
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| H A D | pc87312.c | 209 s->regs[REG_FER] = fer_init[s->config & 0x1f]; in pc87312_soft_reset()
210 s->regs[REG_FAR] = far_init[s->config & 0x1f]; in pc87312_soft_reset()
211 s->regs[REG_PTR] = ptr_init[s->config & 0x1f]; in pc87312_soft_reset()
332 DEFINE_PROP_UINT8("config", PC87312State, config, 1),
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| H A D | piix.c | 54 pic_irq = s->dev.config[PIIX_PIRQCA + pirq]; in piix_set_pci_irq_level_internal()
68 pic_irq = s->dev.config[PIIX_PIRQCA + pirq]; in piix_set_pci_irq_level()
93 int irq = pci_dev->config[PIIX_PIRQCA + pin]; in piix_route_intx_pin_to_irq()
137 uint8_t *pci_conf = d->dev.config; in piix_reset()
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| /qemu/hw/ide/ |
| H A D | pci.c | 111 uint8_t mode = d->config[PCI_CLASS_PROG]; in pci_ide_update_mode()
130 pci_config_set_interrupt_pin(d->config, 0); in pci_ide_update_mode()
166 pci_config_set_interrupt_pin(d->config, 1); in pci_ide_update_mode()
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| H A D | sii3112.c | 258 pci_config_set_interrupt_pin(dev->config, 1); in sii3112_pci_realize()
259 pci_set_byte(dev->config + PCI_CACHE_LINE_SIZE, 8); in sii3112_pci_realize()
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| H A D | via.c | 114 d->config[0x70 + n * 8] |= 0x80; in via_ide_set_irq()
116 d->config[0x70 + n * 8] &= ~0x80; in via_ide_set_irq()
126 uint8_t *pci_conf = pd->config; in via_ide_reset()
165 uint8_t mode = pd->config[PCI_CLASS_PROG]; in via_ide_cfg_read()
201 uint8_t *pci_conf = dev->config; in via_ide_realize()
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| H A D | Kconfig | 1 config IDE_CORE
4 config IDE_BUS
8 config IDE_DEV
12 config IDE_PCI
18 config IDE_ISA
24 config IDE_PIIX
32 config IDE_MACIO
37 config IDE_MMIO
42 config IDE_VIA
52 config AHCI
[all …]
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| H A D | cmd646.c | 61 pd->config[CFR] |= CFR_INTR_CH0; in cmd646_update_dma_interrupts()
63 pd->config[CFR] &= ~CFR_INTR_CH0; in cmd646_update_dma_interrupts()
76 if (pd->config[CFR] & CFR_INTR_CH0) { in cmd646_update_udma_interrupts()
105 val = pci_dev->config[MRDMODE]; in bmdma_read()
112 val = pci_dev->config[UDIDETCR0]; in bmdma_read()
114 val = pci_dev->config[UDIDETCR1]; in bmdma_read()
142 pci_dev->config[MRDMODE] = in bmdma_write()
152 pci_dev->config[UDIDETCR0] = val; in bmdma_write()
203 pd->config[MRDMODE] |= irq_mask; in cmd646_set_irq()
205 pd->config[MRDMODE] &= ~irq_mask; in cmd646_set_irq()
[all …]
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| H A D | piix.c | 110 uint8_t *pci_conf = pd->config; in piix_ide_reset()
155 uint8_t *pci_conf = dev->config; in pci_piix_ide_realize()
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| /qemu/hw/i2c/ |
| H A D | Kconfig | 1 config I2C
4 config I2C_DEVICES
9 config SMBUS
13 config SMBUS_EEPROM
17 config ARM_SBCON_I2C
21 config ACPI_SMBUS
25 config BITBANG_I2C
29 config IMX_I2C
33 config MPC_I2C
41 config PCA954X
[all …]
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| /qemu/hw/i386/ |
| H A D | amd_iommu.c | 240 pci_word_test_and_set_mask(s->pci.dev.config + PCI_STATUS, in amdvi_page_fault()
257 pci_word_test_and_set_mask(s->pci.dev.config + PCI_STATUS, in amdvi_log_devtab_error()
270 pci_word_test_and_set_mask(s->pci.dev.config + PCI_STATUS, in amdvi_log_command_error()
311 pci_word_test_and_set_mask(s->pci.dev.config + PCI_STATUS, in amdvi_log_pagetab_error()
1558 pci_config_set_prog_interface(pdev->config, 0); in amdvi_pci_realize()
1561 pci_set_long(pdev->config + s->capab_offset, AMDVI_CAPAB_FEATURES); in amdvi_pci_realize()
1562 pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_BAR_LOW, in amdvi_pci_realize()
1564 pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_BAR_HIGH, in amdvi_pci_realize()
1566 pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_RANGE, in amdvi_pci_realize()
1568 pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_MISC, 0); in amdvi_pci_realize()
[all …]
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| /qemu/hw/cxl/ |
| H A D | cxl-mailbox-utils.c | 384 pci_get_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID); in cmd_infostat_identify()
386 pci_get_word(pci_dev->config + PCI_SUBSYSTEM_ID); in cmd_infostat_identify()
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| /qemu/hw/fsi/ |
| H A D | Kconfig | 1 config FSI_APB2OPB_ASPEED
6 config FSI
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| /qemu/hw/arm/ |
| H A D | smmuv3-internal.h | 549 #define STE_CFG_S1_ENABLED(config) (config & 0x1) argument
550 #define STE_CFG_S2_ENABLED(config) (config & 0x2) argument
551 #define STE_CFG_ABORT(config) (!(config & 0x4)) argument
552 #define STE_CFG_BYPASS(config) (config == 0x4) argument
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| /qemu/hw/block/ |
| H A D | fdc-internal.h | 124 uint8_t config; member
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| /qemu/docs/system/arm/ |
| H A D | mps2.rst | 60 base address via the SCC CFG_REG6 and CFG_REG7 register config,
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