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Searched refs:ABS (Results 1 – 25 of 103) sorted by last modified time

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/freebsd/sys/dev/sound/pci/
H A Dsolo.c42 #define ABS(x) (((x) < 0)? -(x) : (x)) macro
397 use0 = (ABS(speed - s0) < ABS(speed - s1))? 1 : 0; in ess_calcspeed9()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp184 setOperationAction(ISD::ABS , MVT::i16 , Custom); in X86TargetLowering()
185 setOperationAction(ISD::ABS , MVT::i32 , Custom); in X86TargetLowering()
187 setOperationAction(ISD::ABS , MVT::i64 , Custom); in X86TargetLowering()
1092 setOperationAction(ISD::ABS, VT, Custom); in X86TargetLowering()
1517 setOperationAction(ISD::ABS, MVT::v4i64, Custom); in X86TargetLowering()
1877 setOperationAction(ISD::ABS, VT, Legal); in X86TargetLowering()
2015 setOperationAction(ISD::ABS, VT, Legal); in X86TargetLowering()
17453 case ISD::ABS: in canCombineAsMaskOperation()
43603 if (!Root || Root.getOpcode() != ISD::ABS) in combineBasicSADPattern()
53006 if (LHS.getOpcode() == ISD::ABS && LHS.hasOneUse()) { in combineSetCC()
[all …]
H A DX86TargetTransformInfo.cpp3431 { ISD::ABS, MVT::v32i16, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3432 { ISD::ABS, MVT::v64i8, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3506 { ISD::ABS, MVT::v8i64, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3507 { ISD::ABS, MVT::v4i64, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3508 { ISD::ABS, MVT::v2i64, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3509 { ISD::ABS, MVT::v16i32, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3510 { ISD::ABS, MVT::v8i32, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3511 { ISD::ABS, MVT::v32i16, { 2, 7, 4, 4 } }, in getIntrinsicInstrCost()
3512 { ISD::ABS, MVT::v16i16, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3513 { ISD::ABS, MVT::v64i8, { 2, 7, 4, 4 } }, in getIntrinsicInstrCost()
[all …]
H A DX86InstrFPStack.td263 defm ABS : FPUnary<fabs, MRM_E1, "fabs">;
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp408 setOperationAction(ISD::ABS, MVT::i32, Custom); in RISCVTargetLowering()
412 setOperationAction(ISD::ABS, XLenVT, Legal); in RISCVTargetLowering()
1183 {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX, ISD::ABS}, VT, Custom); in RISCVTargetLowering()
6588 case ISD::ABS: in LowerOperation()
11738 case ISD::ABS: { in ReplaceNodeResults()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1980 case ISD::ABS: return visitABS(N); in visit()
3874 !TLI.isOperationLegalOrCustom(ISD::ABS, VT)) in visitSUB()
4066 if (TLI.isOperationLegalOrCustom(ISD::ABS, VT)) { in visitSUB()
5292 return DAG.getNode(ISD::ABS, DL, VT, N0); in visitABD()
9533 if (TLI.isOperationLegalOrCustom(ISD::ABS, VT)) { in visitXOR()
10918 if (N->getOpcode() != ISD::ABS) in foldABSToABD()
10988 if (N0.getOpcode() == ISD::ABS) in visitABS()
11002 TLI.isTypeDesirableForOp(ISD::ABS, ExtVT) && in visitABS()
11003 hasOperation(ISD::ABS, ExtVT)) { in visitABS()
11007 DAG.getNode(ISD::ABS, DL, ExtVT, in visitABS()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td4904 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", abs>;
5581 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", abs, [HasNoCSSC]>;
9350 defm ABS : OneOperandData<0b001000, "abs", abs>, Requires<[HasCSSC]>;
H A DAArch64ISelLowering.cpp609 setOperationAction(ISD::ABS, MVT::i32, Legal); in AArch64TargetLowering()
610 setOperationAction(ISD::ABS, MVT::i64, Legal); in AArch64TargetLowering()
629 setOperationAction(ISD::ABS, MVT::i32, Custom); in AArch64TargetLowering()
630 setOperationAction(ISD::ABS, MVT::i64, Custom); in AArch64TargetLowering()
1325 setOperationAction(ISD::ABS, VT, Custom); in AArch64TargetLowering()
1734 setOperationAction(ISD::ABS, VT, Legal); in addTypeForNEON()
1857 setOperationAction(ISD::ABS, VT, Custom); in addTypeForFixedLengthSVE()
6358 case ISD::ABS: in LowerOperation()
16527 SDValue ABS = VecReduceOp0; in performVecReduceAddCombineWithUADDLP() local
16529 if (ABS->getOperand(0)->getOpcode() != ISD::SUB || in performVecReduceAddCombineWithUADDLP()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp192 setOperationAction(ISD::ABS, T, Legal); in WebAssemblyTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp175 setOperationAction(ISD::ABS, VT, Legal); in SystemZTargetLowering()
422 setOperationAction(ISD::ABS, VT, Legal); in SystemZTargetLowering()
3445 Op = DAG.getNode(ISD::ABS, DL, Op.getValueType(), Op); in getAbsolute()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp16042 return DAG.getNode(ISD::ABS, dl, V2.getValueType(), V2); in PerformDAGCombine()
16048 return DAG.getNode(ISD::ABS, dl, V1.getValueType(), V1); in PerformDAGCombine()
16054 return DAG.getNode(ISD::ABS, dl, V1.getValueType(), V1); in PerformDAGCombine()
H A DPPCScheduleP7.td243 (instregex "^F(N)?(M)?(R|ADD|SUB|ABS|NEG|NABS|UL)(D|S)?(_rec)?$"),
246 (instregex "^XS(NEG|ABS|NABS|ADD|SUB|MUL)(D|S)P(s)?$"),
260 (instregex "^XV(MAX|MIN|MUL|NEG|ABS|ADD|NABS)(D|S)P$"),
H A DPPCScheduleP8.td173 (instregex "^(F|XS)(ABS|CPSGN|ADD|MUL|NABS|RE|NEG|SUB|SEL|RSQRTE)(D|S)?(P)?(s)?(_rec)?$"),
192 (instregex "^XV(N)?(M)?(RSQRTE|CPSGN|SUB|ADD|ABS|UL|NEG|RE)(A|M)?DP$"),
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp519 {ISD::ABS, ISD::ADD, ISD::ADDC, ISD::ADDE, in NVPTXTargetLowering()
670 setOperationAction(ISD::ABS, Ty, Legal); in NVPTXTargetLowering()
680 setI16x2OperationAction(ISD::ABS, MVT::v2i16, Legal, Custom); in NVPTXTargetLowering()
2721 case ISD::ABS: in LowerOperation()
H A DNVPTXInstrInfo.td867 multiclass ABS<ValueType T, RegisterClass RC, string SizeName> {
872 defm ABS_16 : ABS<i16, Int16Regs, ".s16">;
873 defm ABS_32 : ABS<i32, Int32Regs, ".s32">;
874 defm ABS_64 : ABS<i64, Int64Regs, ".s64">;
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrData.td94 // (ABS).L
232 // Store ABS(basically pointer) as Immdiate to Mem
H A DM68kInstrInfo.td701 // (ABS).L
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1540 {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) { in HexagonTargetLowering()
H A DHexagonISelLoweringHVX.cpp196 setOperationAction(ISD::ABS, T, Legal); in initializeHVXLowering()
292 setOperationAction(ISD::ABS, T, Custom); in initializeHVXLowering()
2870 SDValue Abs = Signed ? DAG.getNode(ISD::ABS, dl, InpTy, Op0) : Op0; in ExpandHvxIntToFp()
3161 case ISD::ABS: in LowerHvxOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp103 setOperationAction(ISD::ABS, MVT::i32, Expand); in CSKYTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM85.td597 def : InstRW<[M85GroupBLat1S], (instregex "V(ABS|NEG)(H|S)$")>;
598 def : InstRW<[M85GroupBLat1D], (instregex "V(ABS|NEG)D$")>;
H A DARMScheduleSwift.td1086 def : InstRW<[SwiftWriteP01OneCycle2x], (instregex "ABS")>;
H A DARMISelLowering.cpp210 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) in addTypeForNEON()
263 setOperationAction(ISD::ABS, VT, Legal); in addMVEVectorTypes()
1632 setTargetDAGCombine(ISD::ABS); in ARMTargetLowering()
4185 return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
12267 case ARM::ABS: in EmitInstrWithCustomInserter()
18865 case ISD::ABS: return PerformABSCombine(N, DCI, Subtarget); in PerformDAGCombine()
H A DARMInstrInfo.td5184 // to implement integer ABS
5185 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
H A DARMInstrNEON.td5657 // ISD::ABS is not legal for v2i64, so VABDL needs to be matched from the
5658 // shift/xor pattern for ABS.

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