/freebsd/sys/dev/sound/pci/ |
H A D | solo.c | 42 #define ABS(x) (((x) < 0)? -(x) : (x)) macro 397 use0 = (ABS(speed - s0) < ABS(speed - s1))? 1 : 0; in ess_calcspeed9()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 184 setOperationAction(ISD::ABS , MVT::i16 , Custom); in X86TargetLowering() 185 setOperationAction(ISD::ABS , MVT::i32 , Custom); in X86TargetLowering() 187 setOperationAction(ISD::ABS , MVT::i64 , Custom); in X86TargetLowering() 1092 setOperationAction(ISD::ABS, VT, Custom); in X86TargetLowering() 1517 setOperationAction(ISD::ABS, MVT::v4i64, Custom); in X86TargetLowering() 1877 setOperationAction(ISD::ABS, VT, Legal); in X86TargetLowering() 2015 setOperationAction(ISD::ABS, VT, Legal); in X86TargetLowering() 17453 case ISD::ABS: in canCombineAsMaskOperation() 43603 if (!Root || Root.getOpcode() != ISD::ABS) in combineBasicSADPattern() 53006 if (LHS.getOpcode() == ISD::ABS && LHS.hasOneUse()) { in combineSetCC() [all …]
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H A D | X86TargetTransformInfo.cpp | 3431 { ISD::ABS, MVT::v32i16, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost() 3432 { ISD::ABS, MVT::v64i8, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost() 3506 { ISD::ABS, MVT::v8i64, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost() 3507 { ISD::ABS, MVT::v4i64, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost() 3508 { ISD::ABS, MVT::v2i64, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost() 3509 { ISD::ABS, MVT::v16i32, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost() 3510 { ISD::ABS, MVT::v8i32, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost() 3511 { ISD::ABS, MVT::v32i16, { 2, 7, 4, 4 } }, in getIntrinsicInstrCost() 3512 { ISD::ABS, MVT::v16i16, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost() 3513 { ISD::ABS, MVT::v64i8, { 2, 7, 4, 4 } }, in getIntrinsicInstrCost() [all …]
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H A D | X86InstrFPStack.td | 263 defm ABS : FPUnary<fabs, MRM_E1, "fabs">;
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 408 setOperationAction(ISD::ABS, MVT::i32, Custom); in RISCVTargetLowering() 412 setOperationAction(ISD::ABS, XLenVT, Legal); in RISCVTargetLowering() 1183 {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX, ISD::ABS}, VT, Custom); in RISCVTargetLowering() 6588 case ISD::ABS: in LowerOperation() 11738 case ISD::ABS: { in ReplaceNodeResults()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 1980 case ISD::ABS: return visitABS(N); in visit() 3874 !TLI.isOperationLegalOrCustom(ISD::ABS, VT)) in visitSUB() 4066 if (TLI.isOperationLegalOrCustom(ISD::ABS, VT)) { in visitSUB() 5292 return DAG.getNode(ISD::ABS, DL, VT, N0); in visitABD() 9533 if (TLI.isOperationLegalOrCustom(ISD::ABS, VT)) { in visitXOR() 10918 if (N->getOpcode() != ISD::ABS) in foldABSToABD() 10988 if (N0.getOpcode() == ISD::ABS) in visitABS() 11002 TLI.isTypeDesirableForOp(ISD::ABS, ExtVT) && in visitABS() 11003 hasOperation(ISD::ABS, ExtVT)) { in visitABS() 11007 DAG.getNode(ISD::ABS, DL, ExtVT, in visitABS() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64InstrInfo.td | 4904 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", abs>; 5581 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", abs, [HasNoCSSC]>; 9350 defm ABS : OneOperandData<0b001000, "abs", abs>, Requires<[HasCSSC]>;
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H A D | AArch64ISelLowering.cpp | 609 setOperationAction(ISD::ABS, MVT::i32, Legal); in AArch64TargetLowering() 610 setOperationAction(ISD::ABS, MVT::i64, Legal); in AArch64TargetLowering() 629 setOperationAction(ISD::ABS, MVT::i32, Custom); in AArch64TargetLowering() 630 setOperationAction(ISD::ABS, MVT::i64, Custom); in AArch64TargetLowering() 1325 setOperationAction(ISD::ABS, VT, Custom); in AArch64TargetLowering() 1734 setOperationAction(ISD::ABS, VT, Legal); in addTypeForNEON() 1857 setOperationAction(ISD::ABS, VT, Custom); in addTypeForFixedLengthSVE() 6358 case ISD::ABS: in LowerOperation() 16527 SDValue ABS = VecReduceOp0; in performVecReduceAddCombineWithUADDLP() local 16529 if (ABS->getOperand(0)->getOpcode() != ISD::SUB || in performVecReduceAddCombineWithUADDLP() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 192 setOperationAction(ISD::ABS, T, Legal); in WebAssemblyTargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 175 setOperationAction(ISD::ABS, VT, Legal); in SystemZTargetLowering() 422 setOperationAction(ISD::ABS, VT, Legal); in SystemZTargetLowering() 3445 Op = DAG.getNode(ISD::ABS, DL, Op.getValueType(), Op); in getAbsolute()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 16042 return DAG.getNode(ISD::ABS, dl, V2.getValueType(), V2); in PerformDAGCombine() 16048 return DAG.getNode(ISD::ABS, dl, V1.getValueType(), V1); in PerformDAGCombine() 16054 return DAG.getNode(ISD::ABS, dl, V1.getValueType(), V1); in PerformDAGCombine()
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H A D | PPCScheduleP7.td | 243 (instregex "^F(N)?(M)?(R|ADD|SUB|ABS|NEG|NABS|UL)(D|S)?(_rec)?$"), 246 (instregex "^XS(NEG|ABS|NABS|ADD|SUB|MUL)(D|S)P(s)?$"), 260 (instregex "^XV(MAX|MIN|MUL|NEG|ABS|ADD|NABS)(D|S)P$"),
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H A D | PPCScheduleP8.td | 173 (instregex "^(F|XS)(ABS|CPSGN|ADD|MUL|NABS|RE|NEG|SUB|SEL|RSQRTE)(D|S)?(P)?(s)?(_rec)?$"), 192 (instregex "^XV(N)?(M)?(RSQRTE|CPSGN|SUB|ADD|ABS|UL|NEG|RE)(A|M)?DP$"),
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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 519 {ISD::ABS, ISD::ADD, ISD::ADDC, ISD::ADDE, in NVPTXTargetLowering() 670 setOperationAction(ISD::ABS, Ty, Legal); in NVPTXTargetLowering() 680 setI16x2OperationAction(ISD::ABS, MVT::v2i16, Legal, Custom); in NVPTXTargetLowering() 2721 case ISD::ABS: in LowerOperation()
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H A D | NVPTXInstrInfo.td | 867 multiclass ABS<ValueType T, RegisterClass RC, string SizeName> { 872 defm ABS_16 : ABS<i16, Int16Regs, ".s16">; 873 defm ABS_32 : ABS<i32, Int32Regs, ".s32">; 874 defm ABS_64 : ABS<i64, Int64Regs, ".s64">;
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
H A D | M68kInstrData.td | 94 // (ABS).L 232 // Store ABS(basically pointer) as Immdiate to Mem
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H A D | M68kInstrInfo.td | 701 // (ABS).L
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 1540 {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) { in HexagonTargetLowering()
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H A D | HexagonISelLoweringHVX.cpp | 196 setOperationAction(ISD::ABS, T, Legal); in initializeHVXLowering() 292 setOperationAction(ISD::ABS, T, Custom); in initializeHVXLowering() 2870 SDValue Abs = Signed ? DAG.getNode(ISD::ABS, dl, InpTy, Op0) : Op0; in ExpandHvxIntToFp() 3161 case ISD::ABS: in LowerHvxOperation()
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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
H A D | CSKYISelLowering.cpp | 103 setOperationAction(ISD::ABS, MVT::i32, Expand); in CSKYTargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMScheduleM85.td | 597 def : InstRW<[M85GroupBLat1S], (instregex "V(ABS|NEG)(H|S)$")>; 598 def : InstRW<[M85GroupBLat1D], (instregex "V(ABS|NEG)D$")>;
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H A D | ARMScheduleSwift.td | 1086 def : InstRW<[SwiftWriteP01OneCycle2x], (instregex "ABS")>;
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H A D | ARMISelLowering.cpp | 210 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) in addTypeForNEON() 263 setOperationAction(ISD::ABS, VT, Legal); in addMVEVectorTypes() 1632 setTargetDAGCombine(ISD::ABS); in ARMTargetLowering() 4185 return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(), in LowerINTRINSIC_WO_CHAIN() 12267 case ARM::ABS: in EmitInstrWithCustomInserter() 18865 case ISD::ABS: return PerformABSCombine(N, DCI, Subtarget); in PerformDAGCombine()
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H A D | ARMInstrInfo.td | 5184 // to implement integer ABS 5185 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
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H A D | ARMInstrNEON.td | 5657 // ISD::ABS is not legal for v2i64, so VABDL needs to be matched from the 5658 // shift/xor pattern for ABS.
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