Home
last modified time | relevance | path

Searched refs:BRU (Results 1 – 25 of 261) sorted by last modified time

1234567891011

/dports/emulators/simh/simh-3.9.0_5/SDS/
H A Dsds_cpu.c784 case BRU: in one_inst()
H A Dsds_defs.h393 HLT, BRU, EOM, EOD = 006, enumerator
H A Dsds_sys.c241 if (I_GETOP (buf[6]) == BRU) in sim_load()
/dports/www/grafana8/grafana-8.3.6/public/gazetteer/
H A Dairports.geojson1 …":{"type":"major","name":"Brussels","abbrev":"BRU","location":"terminal","gps_code":"EBBR","iata_c…
/dports/www/flexget/Flexget-3.2.18/flexget/tests/cassettes/
H A Dtest_imdb.TestImdb.test_lookup1276 KsZGP0ccHa/HuxOHZcN+A3FuofkAqQAK2YJgVsYKg1wHuNmrFxEHAxX602UwS3B/SfDMB82w/BRU
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/PowerPC/
H A DPPCScheduleP8.td27 // 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
394 // to 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.td2387 def BRU : MnemonicAlias<"bru", "j">;
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64SchedTSV110.td36 def TSV110UnitAB : ProcResource<2>; // Int ALU/BRU
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/PowerPC/
H A DPPCScheduleP8.td27 // 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
394 // to 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/
H A DAArch64SchedTSV110.td36 def TSV110UnitAB : ProcResource<2>; // Int ALU/BRU
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/SystemZ/
H A DSystemZInstrInfo.td2387 def BRU : MnemonicAlias<"bru", "j">;
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/PowerPC/
H A DPPCScheduleP8.td27 // 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
394 // to 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.td2387 def BRU : MnemonicAlias<"bru", "j">;
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64SchedTSV110.td36 def TSV110UnitAB : ProcResource<2>; // Int ALU/BRU
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.td2387 def BRU : MnemonicAlias<"bru", "j">;
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64SchedTSV110.td36 def TSV110UnitAB : ProcResource<2>; // Int ALU/BRU
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/PowerPC/
H A DPPCScheduleP8.td27 // 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
394 // to 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
/dports/www/nextcloud-calendar/calendar/js/
H A Dcalendar-appointments-conflict.js.map1 …E,KAARhP,IAEFgP,GADAhP,GAAO,KAILtnB,IACFs2B,GAAQt2B,EAAO,KAGjBs2B,GAAQV,IA/BRU,EAAO98B,GAAGi9B,aAA…
H A Dcalendar-appointments-confirmation.js.map1 …E,KAARhP,IAEFgP,GADAhP,GAAO,KAILtnB,IACFs2B,GAAQt2B,EAAO,KAGjBs2B,GAAQV,IA/BRU,EAAO98B,GAAGi9B,aAA…
/dports/emulators/qemu/qemu-6.2.0/capstone/suite/synctools/tablegen/PPC/
H A DPPCScheduleP8.td28 // 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
387 // to 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
/dports/devel/liblouis/liblouis-3.20.0/tests/braille-specs/
H A Dde-g2-dictionary.yaml1364 - [brust, 'BRU]']
1365 - [brustamputationen, 'BRU]AMPUT!NC']
1366 - [brustbeerbaums, 'BRU]BEERB1MS']
1367 - [brustimplantate, 'BRU]IMPL+TA(']
1370 - [bruyèremaserung, BRU'Y"EREMAS7U]
H A Dde-g1-dictionary.yaml1393 - [brustschnüren, 'BRU]5N8REN']
1394 - [bruststerne, 'BRU]]ERNE']
/dports/lang/gcc12-devel/gcc-12-20211205/gcc/config/mips/
H A Dsr71k.md73 ;; Branch on floating condition go to BRU.
/dports/lang/gcc12-devel/gcc-12-20211205/gcc/config/rs6000/
H A Dpower9.md481 ; Move from LR/CTR are executed in BRU but consume a writeback port from an
H A Dcell.md50 ;; BRU unit: bru(none register stall), bru_cr(cr register stall)

1234567891011