1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9def IsTargetXPLINK64 : Predicate<"Subtarget->isTargetXPLINK64()">; 10def IsTargetELF : Predicate<"Subtarget->isTargetELF()">; 11 12//===----------------------------------------------------------------------===// 13// Stack allocation 14//===----------------------------------------------------------------------===// 15 16// The callseq_start node requires the hasSideEffects flag, even though these 17// instructions are noops on SystemZ. 18let hasNoSchedulingInfo = 1, hasSideEffects = 1 in { 19 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 20 [(callseq_start timm:$amt1, timm:$amt2)]>; 21 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 22 [(callseq_end timm:$amt1, timm:$amt2)]>; 23} 24 25// Takes as input the value of the stack pointer after a dynamic allocation 26// has been made. Sets the output to the address of the dynamically- 27// allocated area itself, skipping the outgoing arguments. 28// 29// This expands to an LA or LAY instruction. We restrict the offset 30// to the range of LA and keep the LAY range in reserve for when 31// the size of the outgoing arguments is added. 32def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src), 33 [(set GR64:$dst, dynalloc12only:$src)]>; 34 35let Defs = [R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1, 36 usesCustomInserter = 1 in 37 def PROBED_ALLOCA : Pseudo<(outs GR64:$dst), 38 (ins GR64:$oldSP, GR64:$space), 39 [(set GR64:$dst, (z_probed_alloca GR64:$oldSP, GR64:$space))]>; 40 41let Defs = [R1D, R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1, 42 hasSideEffects = 1 in 43 def PROBED_STACKALLOC : Pseudo<(outs), (ins i64imm:$stacksize), []>; 44 45//===----------------------------------------------------------------------===// 46// Branch instructions 47//===----------------------------------------------------------------------===// 48 49// Conditional branches. 50let isBranch = 1, isTerminator = 1, Uses = [CC] in { 51 // It's easier for LLVM to handle these branches in their raw BRC/BRCL form 52 // with the condition-code mask being the first operand. It seems friendlier 53 // to use mnemonic forms like JE and JLH when writing out the assembly though. 54 let isCodeGenOnly = 1 in { 55 // An assembler extended mnemonic for BRC. 56 def BRC : CondBranchRI <"j#", 0xA74, z_br_ccmask>; 57 // An assembler extended mnemonic for BRCL. (The extension is "G" 58 // rather than "L" because "JL" is "Jump if Less".) 59 def BRCL : CondBranchRIL<"jg#", 0xC04>; 60 let isIndirectBranch = 1 in { 61 def BC : CondBranchRX<"b#", 0x47>; 62 def BCR : CondBranchRR<"b#r", 0x07>; 63 def BIC : CondBranchRXY<"bi#", 0xe347>, 64 Requires<[FeatureMiscellaneousExtensions2]>; 65 } 66 } 67 68 // Allow using the raw forms directly from the assembler (and occasional 69 // special code generation needs) as well. 70 def BRCAsm : AsmCondBranchRI <"brc", 0xA74>; 71 def BRCLAsm : AsmCondBranchRIL<"brcl", 0xC04>; 72 let isIndirectBranch = 1 in { 73 def BCAsm : AsmCondBranchRX<"bc", 0x47>; 74 def BCRAsm : AsmCondBranchRR<"bcr", 0x07>; 75 def BICAsm : AsmCondBranchRXY<"bic", 0xe347>, 76 Requires<[FeatureMiscellaneousExtensions2]>; 77 } 78 79 // Define AsmParser extended mnemonics for each general condition-code mask 80 // (integer or floating-point) 81 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 82 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 83 def JAsm#V : FixedCondBranchRI <CV<V>, "j#", 0xA74>; 84 def JGAsm#V : FixedCondBranchRIL<CV<V>, "j{g|l}#", 0xC04>; 85 let isIndirectBranch = 1 in { 86 def BAsm#V : FixedCondBranchRX <CV<V>, "b#", 0x47>; 87 def BRAsm#V : FixedCondBranchRR <CV<V>, "b#r", 0x07>; 88 def BIAsm#V : FixedCondBranchRXY<CV<V>, "bi#", 0xe347>, 89 Requires<[FeatureMiscellaneousExtensions2]>; 90 } 91 } 92} 93 94// Unconditional branches. These are in fact simply variants of the 95// conditional branches with the condition mask set to "always". 96let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 97 def J : FixedCondBranchRI <CondAlways, "j", 0xA74, br>; 98 def JG : FixedCondBranchRIL<CondAlways, "j{g|lu}", 0xC04>; 99 let isIndirectBranch = 1 in { 100 def B : FixedCondBranchRX<CondAlways, "b", 0x47>; 101 def BR : FixedCondBranchRR<CondAlways, "br", 0x07, brind>; 102 def BI : FixedCondBranchRXY<CondAlways, "bi", 0xe347, brind>, 103 Requires<[FeatureMiscellaneousExtensions2]>; 104 } 105} 106 107// NOPs. These are again variants of the conditional branches, with the 108// condition mask set to "never". NOP_bare can't be an InstAlias since it 109// would need R0D hard coded which is not part of ADDR64BitRegClass. 110def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>; 111let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, XBD2 = 0 in 112 def NOP_bare : InstRXb<0x47,(outs), (ins), "nop", []>; 113def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>; 114def NOPR_bare : InstAlias<"nopr", (BCRAsm 0, R0D), 0>; 115 116// An alias of BRC 0, label 117def JNOP : InstAlias<"jnop\t$RI2", (BRCAsm 0, brtarget16:$RI2), 0>; 118 119// An alias of BRCL 0, label 120// jgnop on att ; jlnop on hlasm 121def JGNOP : InstAlias<"{jgnop|jlnop}\t$RI2", (BRCLAsm 0, brtarget32:$RI2), 0>; 122 123// Fused compare-and-branch instructions. 124// 125// These instructions do not use or clobber the condition codes. 126// We nevertheless pretend that the relative compare-and-branch 127// instructions clobber CC, so that we can lower them to separate 128// comparisons and BRCLs if the branch ends up being out of range. 129let isBranch = 1, isTerminator = 1 in { 130 // As for normal branches, we handle these instructions internally in 131 // their raw CRJ-like form, but use assembly macros like CRJE when writing 132 // them out. Using the *Pair multiclasses, we also create the raw forms. 133 let Defs = [CC] in { 134 defm CRJ : CmpBranchRIEbPair<"crj", 0xEC76, GR32>; 135 defm CGRJ : CmpBranchRIEbPair<"cgrj", 0xEC64, GR64>; 136 defm CIJ : CmpBranchRIEcPair<"cij", 0xEC7E, GR32, imm32sx8>; 137 defm CGIJ : CmpBranchRIEcPair<"cgij", 0xEC7C, GR64, imm64sx8>; 138 defm CLRJ : CmpBranchRIEbPair<"clrj", 0xEC77, GR32>; 139 defm CLGRJ : CmpBranchRIEbPair<"clgrj", 0xEC65, GR64>; 140 defm CLIJ : CmpBranchRIEcPair<"clij", 0xEC7F, GR32, imm32zx8>; 141 defm CLGIJ : CmpBranchRIEcPair<"clgij", 0xEC7D, GR64, imm64zx8>; 142 } 143 let isIndirectBranch = 1 in { 144 defm CRB : CmpBranchRRSPair<"crb", 0xECF6, GR32>; 145 defm CGRB : CmpBranchRRSPair<"cgrb", 0xECE4, GR64>; 146 defm CIB : CmpBranchRISPair<"cib", 0xECFE, GR32, imm32sx8>; 147 defm CGIB : CmpBranchRISPair<"cgib", 0xECFC, GR64, imm64sx8>; 148 defm CLRB : CmpBranchRRSPair<"clrb", 0xECF7, GR32>; 149 defm CLGRB : CmpBranchRRSPair<"clgrb", 0xECE5, GR64>; 150 defm CLIB : CmpBranchRISPair<"clib", 0xECFF, GR32, imm32zx8>; 151 defm CLGIB : CmpBranchRISPair<"clgib", 0xECFD, GR64, imm64zx8>; 152 } 153 154 // Define AsmParser mnemonics for each integer condition-code mask. 155 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 156 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 157 let Defs = [CC] in { 158 def CRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "crj", 0xEC76, GR32>; 159 def CGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "cgrj", 0xEC64, GR64>; 160 def CIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cij", 0xEC7E, GR32, 161 imm32sx8>; 162 def CGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cgij", 0xEC7C, GR64, 163 imm64sx8>; 164 def CLRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clrj", 0xEC77, GR32>; 165 def CLGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clgrj", 0xEC65, GR64>; 166 def CLIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clij", 0xEC7F, GR32, 167 imm32zx8>; 168 def CLGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clgij", 0xEC7D, GR64, 169 imm64zx8>; 170 } 171 let isIndirectBranch = 1 in { 172 def CRBAsm#V : FixedCmpBranchRRS<ICV<V>, "crb", 0xECF6, GR32>; 173 def CGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "cgrb", 0xECE4, GR64>; 174 def CIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cib", 0xECFE, GR32, 175 imm32sx8>; 176 def CGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cgib", 0xECFC, GR64, 177 imm64sx8>; 178 def CLRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clrb", 0xECF7, GR32>; 179 def CLGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clgrb", 0xECE5, GR64>; 180 def CLIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clib", 0xECFF, GR32, 181 imm32zx8>; 182 def CLGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clgib", 0xECFD, GR64, 183 imm64zx8>; 184 } 185 } 186} 187 188// Decrement a register and branch if it is nonzero. These don't clobber CC, 189// but we might need to split long relative branches into sequences that do. 190let isBranch = 1, isTerminator = 1 in { 191 let Defs = [CC] in { 192 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>; 193 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>; 194 } 195 // This doesn't need to clobber CC since we never need to split it. 196 def BRCTH : BranchUnaryRIL<"brcth", 0xCC6, GRH32>, 197 Requires<[FeatureHighWord]>; 198 199 def BCT : BranchUnaryRX<"bct", 0x46,GR32>; 200 def BCTR : BranchUnaryRR<"bctr", 0x06, GR32>; 201 def BCTG : BranchUnaryRXY<"bctg", 0xE346, GR64>; 202 def BCTGR : BranchUnaryRRE<"bctgr", 0xB946, GR64>; 203} 204 205let isBranch = 1, isTerminator = 1 in { 206 let Defs = [CC] in { 207 def BRXH : BranchBinaryRSI<"brxh", 0x84, GR32>; 208 def BRXLE : BranchBinaryRSI<"brxle", 0x85, GR32>; 209 def BRXHG : BranchBinaryRIEe<"brxhg", 0xEC44, GR64>; 210 def BRXLG : BranchBinaryRIEe<"brxlg", 0xEC45, GR64>; 211 } 212 def BXH : BranchBinaryRS<"bxh", 0x86, GR32>; 213 def BXLE : BranchBinaryRS<"bxle", 0x87, GR32>; 214 def BXHG : BranchBinaryRSY<"bxhg", 0xEB44, GR64>; 215 def BXLEG : BranchBinaryRSY<"bxleg", 0xEB45, GR64>; 216} 217 218//===----------------------------------------------------------------------===// 219// Trap instructions 220//===----------------------------------------------------------------------===// 221 222// Unconditional trap. 223let hasCtrlDep = 1, hasSideEffects = 1 in 224 def Trap : Alias<4, (outs), (ins), [(trap)]>; 225 226// Conditional trap. 227let hasCtrlDep = 1, Uses = [CC], hasSideEffects = 1 in 228 def CondTrap : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 229 230// Fused compare-and-trap instructions. 231let hasCtrlDep = 1, hasSideEffects = 1 in { 232 // These patterns work the same way as for compare-and-branch. 233 defm CRT : CmpBranchRRFcPair<"crt", 0xB972, GR32>; 234 defm CGRT : CmpBranchRRFcPair<"cgrt", 0xB960, GR64>; 235 defm CLRT : CmpBranchRRFcPair<"clrt", 0xB973, GR32>; 236 defm CLGRT : CmpBranchRRFcPair<"clgrt", 0xB961, GR64>; 237 defm CIT : CmpBranchRIEaPair<"cit", 0xEC72, GR32, imm32sx16>; 238 defm CGIT : CmpBranchRIEaPair<"cgit", 0xEC70, GR64, imm64sx16>; 239 defm CLFIT : CmpBranchRIEaPair<"clfit", 0xEC73, GR32, imm32zx16>; 240 defm CLGIT : CmpBranchRIEaPair<"clgit", 0xEC71, GR64, imm64zx16>; 241 let Predicates = [FeatureMiscellaneousExtensions] in { 242 defm CLT : CmpBranchRSYbPair<"clt", 0xEB23, GR32>; 243 defm CLGT : CmpBranchRSYbPair<"clgt", 0xEB2B, GR64>; 244 } 245 246 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 247 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 248 def CRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "crt", 0xB972, GR32>; 249 def CGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "cgrt", 0xB960, GR64>; 250 def CLRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clrt", 0xB973, GR32>; 251 def CLGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clgrt", 0xB961, GR64>; 252 def CITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cit", 0xEC72, GR32, 253 imm32sx16>; 254 def CGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cgit", 0xEC70, GR64, 255 imm64sx16>; 256 def CLFITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clfit", 0xEC73, GR32, 257 imm32zx16>; 258 def CLGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clgit", 0xEC71, GR64, 259 imm64zx16>; 260 let Predicates = [FeatureMiscellaneousExtensions] in { 261 def CLTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clt", 0xEB23, GR32>; 262 def CLGTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clgt", 0xEB2B, GR64>; 263 } 264 } 265} 266 267//===----------------------------------------------------------------------===// 268// Call and return instructions 269//===----------------------------------------------------------------------===// 270 271// Define the general form of the call instructions for the asm parser. 272// These instructions don't hard-code %r14 as the return address register. 273let isCall = 1, Defs = [CC] in { 274 def BRAS : CallRI <"bras", 0xA75>; 275 def BRASL : CallRIL<"brasl", 0xC05>; 276 def BAS : CallRX <"bas", 0x4D>; 277 def BASR : CallRR <"basr", 0x0D>; 278} 279 280// z/OS XPLINK 281let Predicates = [IsTargetXPLINK64] in { 282 let isCall = 1, Defs = [R7D, CC], Uses = [FPC] in { 283 def CallBRASL_XPLINK64 : Alias<8, (outs), (ins pcrel32:$I2, variable_ops), 284 [(z_call pcrel32:$I2)]>; 285 def CallBASR_XPLINK64 : Alias<4, (outs), (ins ADDR64:$R2, variable_ops), 286 [(z_call ADDR64:$R2)]>; 287 } 288} 289 290// Regular calls. 291// z/Linux ELF 292let Predicates = [IsTargetELF] in { 293 let isCall = 1, Defs = [R14D, CC], Uses = [FPC] in { 294 def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops), 295 [(z_call pcrel32:$I2)]>; 296 def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops), 297 [(z_call ADDR64:$R2)]>; 298 } 299 300 // TLS calls. These will be lowered into a call to __tls_get_offset, 301 // with an extra relocation specifying the TLS symbol. 302 let isCall = 1, Defs = [R14D, CC] in { 303 def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 304 [(z_tls_gdcall tglobaltlsaddr:$I2)]>; 305 def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 306 [(z_tls_ldcall tglobaltlsaddr:$I2)]>; 307 } 308} 309 310// Sibling calls. Indirect sibling calls must be via R6 for XPLink, 311// R1 used for ELF 312let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 313 def CallJG : Alias<6, (outs), (ins pcrel32:$I2), 314 [(z_sibcall pcrel32:$I2)]>; 315 def CallBR : Alias<2, (outs), (ins ADDR64:$R2), 316 [(z_sibcall ADDR64:$R2)]>; 317} 318 319// Conditional sibling calls. 320let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in { 321 def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1, 322 pcrel32:$I2), []>; 323 def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1, 324 ADDR64:$R2), []>; 325} 326 327// Fused compare and conditional sibling calls. 328let isCall = 1, isTerminator = 1, isReturn = 1 in { 329 def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>; 330 def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>; 331 def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3, ADDR64:$R4), []>; 332 def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3, ADDR64:$R4), []>; 333 def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>; 334 def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>; 335 def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3, ADDR64:$R4), []>; 336 def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3, ADDR64:$R4), []>; 337} 338 339// A return instruction (br %r14) for ELF and (b 2 %r7) for XPLink. 340let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 341 def Return : Alias<2, (outs), (ins), [(z_retflag)]>; 342 343// A conditional return instruction (bcr <cond>, %r14). 344let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 345 def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 346 347// Fused compare and conditional returns. 348let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in { 349 def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 350 def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 351 def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 352 def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 353 def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 354 def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 355 def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 356 def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 357} 358 359//===----------------------------------------------------------------------===// 360// Select instructions 361//===----------------------------------------------------------------------===// 362 363def Select32 : SelectWrapper<i32, GR32>, 364 Requires<[FeatureNoLoadStoreOnCond]>; 365def Select64 : SelectWrapper<i64, GR64>, 366 Requires<[FeatureNoLoadStoreOnCond]>; 367 368// We don't define 32-bit Mux stores if we don't have STOCFH, because the 369// low-only STOC should then always be used if possible. 370defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8, 371 nonvolatile_anyextloadi8, bdxaddr20only>, 372 Requires<[FeatureHighWord]>; 373defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16, 374 nonvolatile_anyextloadi16, bdxaddr20only>, 375 Requires<[FeatureHighWord]>; 376defm CondStore32Mux : CondStores<GRX32, simple_store, 377 simple_load, bdxaddr20only>, 378 Requires<[FeatureLoadStoreOnCond2]>; 379defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8, 380 nonvolatile_anyextloadi8, bdxaddr20only>; 381defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16, 382 nonvolatile_anyextloadi16, bdxaddr20only>; 383defm CondStore32 : CondStores<GR32, simple_store, 384 simple_load, bdxaddr20only>; 385 386defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8, 387 nonvolatile_anyextloadi8, bdxaddr20only>; 388defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16, 389 nonvolatile_anyextloadi16, bdxaddr20only>; 390defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32, 391 nonvolatile_anyextloadi32, bdxaddr20only>; 392defm CondStore64 : CondStores<GR64, simple_store, 393 simple_load, bdxaddr20only>; 394 395//===----------------------------------------------------------------------===// 396// Move instructions 397//===----------------------------------------------------------------------===// 398 399// Register moves. 400def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>; 401def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>; 402 403let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 404 def LTR : UnaryRR <"ltr", 0x12, null_frag, GR32, GR32>; 405 def LTGR : UnaryRRE<"ltgr", 0xB902, null_frag, GR64, GR64>; 406} 407 408let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 409 def PAIR128 : Pseudo<(outs GR128:$dst), (ins GR64:$hi, GR64:$lo), []>; 410 411// Immediate moves. 412let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 413 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF, 414 // deopending on the choice of register. 415 def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>, 416 Requires<[FeatureHighWord]>; 417 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; 418 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; 419 420 // Other 16-bit immediates. 421 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>; 422 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>; 423 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>; 424 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>; 425 426 // 32-bit immediates. 427 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>; 428 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; 429 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; 430} 431 432// Register loads. 433let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in { 434 // Expands to L, LY or LFH, depending on the choice of register. 435 def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>, 436 Requires<[FeatureHighWord]>; 437 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>; 438 def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>, 439 Requires<[FeatureHighWord]>; 440 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>; 441 442 // These instructions are split after register allocation, so we don't 443 // want a custom inserter. 444 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 445 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src), 446 [(set GR128:$dst, (load bdxaddr20only128:$src))]>; 447 } 448} 449let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 450 def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>; 451 def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>; 452} 453 454let canFoldAsLoad = 1 in { 455 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>; 456 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>; 457} 458 459// Load and zero rightmost byte. 460let Predicates = [FeatureLoadAndZeroRightmostByte] in { 461 def LZRF : UnaryRXY<"lzrf", 0xE33B, null_frag, GR32, 4>; 462 def LZRG : UnaryRXY<"lzrg", 0xE32A, null_frag, GR64, 8>; 463 def : Pat<(and (i32 (load bdxaddr20only:$src)), 0xffffff00), 464 (LZRF bdxaddr20only:$src)>; 465 def : Pat<(and (i64 (load bdxaddr20only:$src)), 0xffffffffffffff00), 466 (LZRG bdxaddr20only:$src)>; 467} 468 469// Load and trap. 470let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 471 def LAT : UnaryRXY<"lat", 0xE39F, null_frag, GR32, 4>; 472 def LFHAT : UnaryRXY<"lfhat", 0xE3C8, null_frag, GRH32, 4>; 473 def LGAT : UnaryRXY<"lgat", 0xE385, null_frag, GR64, 8>; 474} 475 476// Register stores. 477let SimpleBDXStore = 1, mayStore = 1 in { 478 // Expands to ST, STY or STFH, depending on the choice of register. 479 def STMux : StoreRXYPseudo<store, GRX32, 4>, 480 Requires<[FeatureHighWord]>; 481 defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>; 482 def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>, 483 Requires<[FeatureHighWord]>; 484 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>; 485 486 // These instructions are split after register allocation, so we don't 487 // want a custom inserter. 488 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 489 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst), 490 [(store GR128:$src, bdxaddr20only128:$dst)]>; 491 } 492} 493def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>; 494def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>; 495 496// 8-bit immediate stores to 8-bit fields. 497defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>; 498 499// 16-bit immediate stores to 16-, 32- or 64-bit fields. 500def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>; 501def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>; 502def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>; 503 504// Memory-to-memory moves. 505let mayLoad = 1, mayStore = 1 in 506 defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>; 507let mayLoad = 1, mayStore = 1, Defs = [CC] in { 508 def MVCL : SideEffectBinaryMemMemRR<"mvcl", 0x0E, GR128, GR128>; 509 def MVCLE : SideEffectTernaryMemMemRS<"mvcle", 0xA8, GR128, GR128>; 510 def MVCLU : SideEffectTernaryMemMemRSY<"mvclu", 0xEB8E, GR128, GR128>; 511} 512 513// Move right. 514let Predicates = [FeatureMiscellaneousExtensions3], 515 mayLoad = 1, mayStore = 1, Uses = [R0L] in 516 def MVCRL : SideEffectBinarySSE<"mvcrl", 0xE50A>; 517 518// String moves. 519let mayLoad = 1, mayStore = 1, Defs = [CC] in 520 defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>; 521 522//===----------------------------------------------------------------------===// 523// Conditional move instructions 524//===----------------------------------------------------------------------===// 525 526let Predicates = [FeatureMiscellaneousExtensions3], Uses = [CC] in { 527 // Select. 528 let isCommutable = 1 in { 529 // Expands to SELR or SELFHR or a branch-and-move sequence, 530 // depending on the choice of registers. 531 def SELRMux : CondBinaryRRFaPseudo<"MUXselr", GRX32, GRX32, GRX32>; 532 defm SELFHR : CondBinaryRRFaPair<"selfhr", 0xB9C0, GRH32, GRH32, GRH32>; 533 defm SELR : CondBinaryRRFaPair<"selr", 0xB9F0, GR32, GR32, GR32>; 534 defm SELGR : CondBinaryRRFaPair<"selgr", 0xB9E3, GR64, GR64, GR64>; 535 } 536 537 // Define AsmParser extended mnemonics for each general condition-code mask. 538 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 539 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 540 def SELRAsm#V : FixedCondBinaryRRFa<CV<V>, "selr", 0xB9F0, 541 GR32, GR32, GR32>; 542 def SELFHRAsm#V : FixedCondBinaryRRFa<CV<V>, "selfhr", 0xB9C0, 543 GRH32, GRH32, GRH32>; 544 def SELGRAsm#V : FixedCondBinaryRRFa<CV<V>, "selgr", 0xB9E3, 545 GR64, GR64, GR64>; 546 } 547} 548 549let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in { 550 // Load immediate on condition. Matched via DAG pattern and created 551 // by the PeepholeOptimizer via FoldImmediate. 552 553 // Expands to LOCHI or LOCHHI, depending on the choice of register. 554 def LOCHIMux : CondBinaryRIEPseudo<GRX32, imm32sx16>; 555 defm LOCHHI : CondBinaryRIEPair<"lochhi", 0xEC4E, GRH32, imm32sx16>; 556 defm LOCHI : CondBinaryRIEPair<"lochi", 0xEC42, GR32, imm32sx16>; 557 defm LOCGHI : CondBinaryRIEPair<"locghi", 0xEC46, GR64, imm64sx16>; 558 559 // Move register on condition. Matched via DAG pattern and 560 // created by early if-conversion. 561 let isCommutable = 1 in { 562 // Expands to LOCR or LOCFHR or a branch-and-move sequence, 563 // depending on the choice of registers. 564 def LOCRMux : CondBinaryRRFPseudo<"MUXlocr", GRX32, GRX32>; 565 defm LOCFHR : CondBinaryRRFPair<"locfhr", 0xB9E0, GRH32, GRH32>; 566 } 567 568 // Load on condition. Matched via DAG pattern. 569 // Expands to LOC or LOCFH, depending on the choice of register. 570 defm LOCMux : CondUnaryRSYPseudoAndMemFold<"MUXloc", simple_load, GRX32, 4>; 571 defm LOCFH : CondUnaryRSYPair<"locfh", 0xEBE0, simple_load, GRH32, 4>; 572 573 // Store on condition. Expanded from CondStore* pseudos. 574 // Expands to STOC or STOCFH, depending on the choice of register. 575 def STOCMux : CondStoreRSYPseudo<GRX32, 4>; 576 defm STOCFH : CondStoreRSYPair<"stocfh", 0xEBE1, GRH32, 4>; 577 578 // Define AsmParser extended mnemonics for each general condition-code mask. 579 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 580 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 581 def LOCHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochi", 0xEC42, GR32, 582 imm32sx16>; 583 def LOCGHIAsm#V : FixedCondBinaryRIE<CV<V>, "locghi", 0xEC46, GR64, 584 imm64sx16>; 585 def LOCHHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochhi", 0xEC4E, GRH32, 586 imm32sx16>; 587 def LOCFHRAsm#V : FixedCondBinaryRRF<CV<V>, "locfhr", 0xB9E0, GRH32, GRH32>; 588 def LOCFHAsm#V : FixedCondUnaryRSY<CV<V>, "locfh", 0xEBE0, GRH32, 4>; 589 def STOCFHAsm#V : FixedCondStoreRSY<CV<V>, "stocfh", 0xEBE1, GRH32, 4>; 590 } 591} 592 593let Predicates = [FeatureLoadStoreOnCond], Uses = [CC] in { 594 // Move register on condition. Matched via DAG pattern and 595 // created by early if-conversion. 596 let isCommutable = 1 in { 597 defm LOCR : CondBinaryRRFPair<"locr", 0xB9F2, GR32, GR32>; 598 defm LOCGR : CondBinaryRRFPair<"locgr", 0xB9E2, GR64, GR64>; 599 } 600 601 // Load on condition. Matched via DAG pattern. 602 defm LOC : CondUnaryRSYPair<"loc", 0xEBF2, simple_load, GR32, 4>; 603 defm LOCG : CondUnaryRSYPairAndMemFold<"locg", 0xEBE2, simple_load, GR64, 8>; 604 605 // Store on condition. Expanded from CondStore* pseudos. 606 defm STOC : CondStoreRSYPair<"stoc", 0xEBF3, GR32, 4>; 607 defm STOCG : CondStoreRSYPair<"stocg", 0xEBE3, GR64, 8>; 608 609 // Define AsmParser extended mnemonics for each general condition-code mask. 610 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 611 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 612 def LOCRAsm#V : FixedCondBinaryRRF<CV<V>, "locr", 0xB9F2, GR32, GR32>; 613 def LOCGRAsm#V : FixedCondBinaryRRF<CV<V>, "locgr", 0xB9E2, GR64, GR64>; 614 def LOCAsm#V : FixedCondUnaryRSY<CV<V>, "loc", 0xEBF2, GR32, 4>; 615 def LOCGAsm#V : FixedCondUnaryRSY<CV<V>, "locg", 0xEBE2, GR64, 8>; 616 def STOCAsm#V : FixedCondStoreRSY<CV<V>, "stoc", 0xEBF3, GR32, 4>; 617 def STOCGAsm#V : FixedCondStoreRSY<CV<V>, "stocg", 0xEBE3, GR64, 8>; 618 } 619} 620//===----------------------------------------------------------------------===// 621// Sign extensions 622//===----------------------------------------------------------------------===// 623// 624// Note that putting these before zero extensions mean that we will prefer 625// them for anyextload*. There's not really much to choose between the two 626// either way, but signed-extending loads have a short LH and a long LHY, 627// while zero-extending loads have only the long LLH. 628// 629//===----------------------------------------------------------------------===// 630 631// 32-bit extensions from registers. 632def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>; 633def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>; 634 635// 64-bit extensions from registers. 636def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>; 637def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>; 638def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>; 639 640let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 641 def LTGFR : UnaryRRE<"ltgfr", 0xB912, null_frag, GR64, GR32>; 642 643// Match 32-to-64-bit sign extensions in which the source is already 644// in a 64-bit register. 645def : Pat<(sext_inreg GR64:$src, i32), 646 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 647 648// 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH, 649// depending on the choice of register. 650def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>, 651 Requires<[FeatureHighWord]>; 652def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>; 653def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>, 654 Requires<[FeatureHighWord]>; 655 656// 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH, 657// depending on the choice of register. 658def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>, 659 Requires<[FeatureHighWord]>; 660defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>; 661def LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>, 662 Requires<[FeatureHighWord]>; 663def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>; 664 665// 64-bit extensions from memory. 666def LGB : UnaryRXY<"lgb", 0xE377, asextloadi8, GR64, 1>; 667def LGH : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>; 668def LGF : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>; 669def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>; 670def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>; 671let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 672 def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>; 673 674//===----------------------------------------------------------------------===// 675// Zero extensions 676//===----------------------------------------------------------------------===// 677 678// 32-bit extensions from registers. 679 680// Expands to LLCR or RISB[LH]G, depending on the choice of registers. 681def LLCRMux : UnaryRRPseudo<"llcr", zext8, GRX32, GRX32>, 682 Requires<[FeatureHighWord]>; 683def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>; 684// Expands to LLHR or RISB[LH]G, depending on the choice of registers. 685def LLHRMux : UnaryRRPseudo<"llhr", zext16, GRX32, GRX32>, 686 Requires<[FeatureHighWord]>; 687def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>; 688 689// 64-bit extensions from registers. 690def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>; 691def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>; 692def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>; 693 694// Match 32-to-64-bit zero extensions in which the source is already 695// in a 64-bit register. 696def : Pat<(and GR64:$src, 0xffffffff), 697 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 698 699// 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH, 700// depending on the choice of register. 701def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>, 702 Requires<[FeatureHighWord]>; 703def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>; 704def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GRH32, 1>, 705 Requires<[FeatureHighWord]>; 706 707// 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH, 708// depending on the choice of register. 709def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>, 710 Requires<[FeatureHighWord]>; 711def LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>; 712def LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GRH32, 2>, 713 Requires<[FeatureHighWord]>; 714def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>; 715 716// 64-bit extensions from memory. 717def LLGC : UnaryRXY<"llgc", 0xE390, azextloadi8, GR64, 1>; 718def LLGH : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>; 719def LLGF : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>; 720def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>; 721def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>; 722 723// 31-to-64-bit zero extensions. 724def LLGTR : UnaryRRE<"llgtr", 0xB917, null_frag, GR64, GR64>; 725def LLGT : UnaryRXY<"llgt", 0xE317, null_frag, GR64, 4>; 726def : Pat<(and GR64:$src, 0x7fffffff), 727 (LLGTR GR64:$src)>; 728def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0x7fffffff), 729 (LLGT bdxaddr20only:$src)>; 730 731// Load and zero rightmost byte. 732let Predicates = [FeatureLoadAndZeroRightmostByte] in { 733 def LLZRGF : UnaryRXY<"llzrgf", 0xE33A, null_frag, GR64, 4>; 734 def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0xffffff00), 735 (LLZRGF bdxaddr20only:$src)>; 736} 737 738// Load and trap. 739let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 740 def LLGFAT : UnaryRXY<"llgfat", 0xE39D, null_frag, GR64, 4>; 741 def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>; 742} 743 744// Extend GR64s to GR128s. 745let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 746 def ZEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 747 748//===----------------------------------------------------------------------===// 749// "Any" extensions 750//===----------------------------------------------------------------------===// 751 752// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. 753def : Pat<(i64 (anyext GR32:$src)), 754 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>; 755 756// Extend GR64s to GR128s. 757let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 758 def AEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 759 760//===----------------------------------------------------------------------===// 761// Truncations 762//===----------------------------------------------------------------------===// 763 764// Truncations of 64-bit registers to 32-bit registers. 765def : Pat<(i32 (trunc GR64:$src)), 766 (EXTRACT_SUBREG GR64:$src, subreg_l32)>; 767 768// Truncations of 32-bit registers to 8-bit memory. STCMux expands to 769// STC, STCY or STCH, depending on the choice of register. 770def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>, 771 Requires<[FeatureHighWord]>; 772defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>; 773def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>, 774 Requires<[FeatureHighWord]>; 775 776// Truncations of 32-bit registers to 16-bit memory. STHMux expands to 777// STH, STHY or STHH, depending on the choice of register. 778def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>, 779 Requires<[FeatureHighWord]>; 780defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>; 781def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>, 782 Requires<[FeatureHighWord]>; 783def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; 784 785// Truncations of 64-bit registers to memory. 786defm : StoreGR64Pair<STC, STCY, truncstorei8>; 787defm : StoreGR64Pair<STH, STHY, truncstorei16>; 788def : StoreGR64PC<STHRL, aligned_truncstorei16>; 789defm : StoreGR64Pair<ST, STY, truncstorei32>; 790def : StoreGR64PC<STRL, aligned_truncstorei32>; 791 792// Store characters under mask -- not (yet) used for codegen. 793defm STCM : StoreBinaryRSPair<"stcm", 0xBE, 0xEB2D, GR32, 0>; 794def STCMH : StoreBinaryRSY<"stcmh", 0xEB2C, GRH32, 0>; 795 796//===----------------------------------------------------------------------===// 797// Multi-register moves 798//===----------------------------------------------------------------------===// 799 800// Multi-register loads. 801defm LM : LoadMultipleRSPair<"lm", 0x98, 0xEB98, GR32>; 802def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; 803def LMH : LoadMultipleRSY<"lmh", 0xEB96, GRH32>; 804def LMD : LoadMultipleSSe<"lmd", 0xEF, GR64>; 805 806// Multi-register stores. 807defm STM : StoreMultipleRSPair<"stm", 0x90, 0xEB90, GR32>; 808def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; 809def STMH : StoreMultipleRSY<"stmh", 0xEB26, GRH32>; 810 811//===----------------------------------------------------------------------===// 812// Byte swaps 813//===----------------------------------------------------------------------===// 814 815// Byte-swapping register moves. 816def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>; 817def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>; 818 819// Byte-swapping loads. 820def LRVH : UnaryRXY<"lrvh", 0xE31F, z_loadbswap16, GR32, 2>; 821def LRV : UnaryRXY<"lrv", 0xE31E, z_loadbswap32, GR32, 4>; 822def LRVG : UnaryRXY<"lrvg", 0xE30F, z_loadbswap64, GR64, 8>; 823 824// Byte-swapping stores. 825def STRVH : StoreRXY<"strvh", 0xE33F, z_storebswap16, GR32, 2>; 826def STRV : StoreRXY<"strv", 0xE33E, z_storebswap32, GR32, 4>; 827def STRVG : StoreRXY<"strvg", 0xE32F, z_storebswap64, GR64, 8>; 828 829// Byte-swapping memory-to-memory moves. 830let mayLoad = 1, mayStore = 1 in 831 def MVCIN : SideEffectBinarySSa<"mvcin", 0xE8>; 832 833//===----------------------------------------------------------------------===// 834// Load address instructions 835//===----------------------------------------------------------------------===// 836 837// Load BDX-style addresses. 838let isAsCheapAsAMove = 1, isReMaterializable = 1 in 839 defm LA : LoadAddressRXPair<"la", 0x41, 0xE371, bitconvert>; 840 841// Load a PC-relative address. There's no version of this instruction 842// with a 16-bit offset, so there's no relaxation. 843let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in 844 def LARL : LoadAddressRIL<"larl", 0xC00, bitconvert>; 845 846// Load the Global Offset Table address. This will be lowered into a 847// larl $R1, _GLOBAL_OFFSET_TABLE_ 848// instruction. 849def GOT : Alias<6, (outs GR64:$R1), (ins), 850 [(set GR64:$R1, (global_offset_table))]>; 851 852//===----------------------------------------------------------------------===// 853// Absolute and Negation 854//===----------------------------------------------------------------------===// 855 856let Defs = [CC] in { 857 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 858 def LPR : UnaryRR <"lpr", 0x10, abs, GR32, GR32>; 859 def LPGR : UnaryRRE<"lpgr", 0xB900, abs, GR64, GR64>; 860 } 861 let CCValues = 0xE, CompareZeroCCMask = 0xE in 862 def LPGFR : UnaryRRE<"lpgfr", 0xB910, null_frag, GR64, GR32>; 863} 864defm : SXU<abs, LPGFR>; 865 866let Defs = [CC] in { 867 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 868 def LNR : UnaryRR <"lnr", 0x11, z_inegabs, GR32, GR32>; 869 def LNGR : UnaryRRE<"lngr", 0xB901, z_inegabs, GR64, GR64>; 870 } 871 let CCValues = 0xE, CompareZeroCCMask = 0xE in 872 def LNGFR : UnaryRRE<"lngfr", 0xB911, null_frag, GR64, GR32>; 873} 874defm : SXU<z_inegabs, LNGFR>; 875 876let Defs = [CC] in { 877 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 878 def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>; 879 def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>; 880 } 881 let CCValues = 0xE, CompareZeroCCMask = 0xE in 882 def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>; 883} 884defm : SXU<ineg, LCGFR>; 885 886//===----------------------------------------------------------------------===// 887// Insertion 888//===----------------------------------------------------------------------===// 889 890let isCodeGenOnly = 1 in 891 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>; 892defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>; 893 894defm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>; 895defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>; 896 897defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>; 898defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>; 899 900// Insert characters under mask -- not (yet) used for codegen. 901let Defs = [CC] in { 902 defm ICM : TernaryRSPair<"icm", 0xBF, 0xEB81, GR32, 0>; 903 def ICMH : TernaryRSY<"icmh", 0xEB80, GRH32, 0>; 904} 905 906// Insertions of a 16-bit immediate, leaving other bits unaffected. 907// We don't have or_as_insert equivalents of these operations because 908// OI is available instead. 909// 910// IIxMux expands to II[LH]x, depending on the choice of register. 911def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>, 912 Requires<[FeatureHighWord]>; 913def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>, 914 Requires<[FeatureHighWord]>; 915def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; 916def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; 917def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>; 918def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>; 919def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>; 920def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>; 921def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>; 922def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>; 923 924// ...likewise for 32-bit immediates. For GR32s this is a general 925// full-width move. (We use IILF rather than something like LLILF 926// for 32-bit moves because IILF leaves the upper 32 bits of the 927// GR64 unchanged.) 928let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 929 def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>, 930 Requires<[FeatureHighWord]>; 931 def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; 932 def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>; 933} 934def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>; 935def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>; 936 937// An alternative model of inserthf, with the first operand being 938// a zero-extended value. 939def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), 940 (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 941 imm64hf32:$imm)>; 942 943//===----------------------------------------------------------------------===// 944// Addition 945//===----------------------------------------------------------------------===// 946 947// Addition producing a signed overflow flag. 948let Defs = [CC], CCValues = 0xF, CCIfNoSignedWrap = 1 in { 949 // Addition of a register. 950 let isCommutable = 1 in { 951 defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, z_sadd, GR32, GR32>; 952 defm AGR : BinaryRREAndK<"agr", 0xB908, 0xB9E8, z_sadd, GR64, GR64>; 953 } 954 def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>; 955 956 // Addition to a high register. 957 def AHHHR : BinaryRRFa<"ahhhr", 0xB9C8, null_frag, GRH32, GRH32, GRH32>, 958 Requires<[FeatureHighWord]>; 959 def AHHLR : BinaryRRFa<"ahhlr", 0xB9D8, null_frag, GRH32, GRH32, GR32>, 960 Requires<[FeatureHighWord]>; 961 962 // Addition of signed 16-bit immediates. 963 defm AHIMux : BinaryRIAndKPseudo<"ahimux", z_sadd, GRX32, imm32sx16>; 964 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, z_sadd, GR32, imm32sx16>; 965 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, z_sadd, GR64, imm64sx16>; 966 967 // Addition of signed 32-bit immediates. 968 def AFIMux : BinaryRIPseudo<z_sadd, GRX32, simm32>, 969 Requires<[FeatureHighWord]>; 970 def AFI : BinaryRIL<"afi", 0xC29, z_sadd, GR32, simm32>; 971 def AIH : BinaryRIL<"aih", 0xCC8, z_sadd, GRH32, simm32>, 972 Requires<[FeatureHighWord]>; 973 def AGFI : BinaryRIL<"agfi", 0xC28, z_sadd, GR64, imm64sx32>; 974 975 // Addition of memory. 976 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, z_sadd, GR32, asextloadi16, 2>; 977 defm A : BinaryRXPairAndPseudo<"a", 0x5A, 0xE35A, z_sadd, GR32, load, 4>; 978 def AGH : BinaryRXY<"agh", 0xE338, z_sadd, GR64, asextloadi16, 2>, 979 Requires<[FeatureMiscellaneousExtensions2]>; 980 def AGF : BinaryRXY<"agf", 0xE318, z_sadd, GR64, asextloadi32, 4>; 981 defm AG : BinaryRXYAndPseudo<"ag", 0xE308, z_sadd, GR64, load, 8>; 982 983 // Addition to memory. 984 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>; 985 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>; 986} 987defm : SXB<z_sadd, GR64, AGFR>; 988 989// Addition producing a carry. 990let Defs = [CC], CCValues = 0xF, IsLogical = 1 in { 991 // Addition of a register. 992 let isCommutable = 1 in { 993 defm ALR : BinaryRRAndK<"alr", 0x1E, 0xB9FA, z_uadd, GR32, GR32>; 994 defm ALGR : BinaryRREAndK<"algr", 0xB90A, 0xB9EA, z_uadd, GR64, GR64>; 995 } 996 def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>; 997 998 // Addition to a high register. 999 def ALHHHR : BinaryRRFa<"alhhhr", 0xB9CA, null_frag, GRH32, GRH32, GRH32>, 1000 Requires<[FeatureHighWord]>; 1001 def ALHHLR : BinaryRRFa<"alhhlr", 0xB9DA, null_frag, GRH32, GRH32, GR32>, 1002 Requires<[FeatureHighWord]>; 1003 1004 // Addition of signed 16-bit immediates. 1005 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, z_uadd, GR32, imm32sx16>, 1006 Requires<[FeatureDistinctOps]>; 1007 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, z_uadd, GR64, imm64sx16>, 1008 Requires<[FeatureDistinctOps]>; 1009 1010 // Addition of unsigned 32-bit immediates. 1011 def ALFI : BinaryRIL<"alfi", 0xC2B, z_uadd, GR32, uimm32>; 1012 def ALGFI : BinaryRIL<"algfi", 0xC2A, z_uadd, GR64, imm64zx32>; 1013 1014 // Addition of signed 32-bit immediates. 1015 def ALSIH : BinaryRIL<"alsih", 0xCCA, null_frag, GRH32, simm32>, 1016 Requires<[FeatureHighWord]>; 1017 1018 // Addition of memory. 1019 defm AL : BinaryRXPairAndPseudo<"al", 0x5E, 0xE35E, z_uadd, GR32, load, 4>; 1020 def ALGF : BinaryRXY<"algf", 0xE31A, z_uadd, GR64, azextloadi32, 4>; 1021 defm ALG : BinaryRXYAndPseudo<"alg", 0xE30A, z_uadd, GR64, load, 8>; 1022 1023 // Addition to memory. 1024 def ALSI : BinarySIY<"alsi", 0xEB6E, null_frag, imm32sx8>; 1025 def ALGSI : BinarySIY<"algsi", 0xEB7E, null_frag, imm64sx8>; 1026} 1027defm : ZXB<z_uadd, GR64, ALGFR>; 1028 1029// Addition producing and using a carry. 1030let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in { 1031 // Addition of a register. 1032 def ALCR : BinaryRRE<"alcr", 0xB998, z_addcarry, GR32, GR32>; 1033 def ALCGR : BinaryRRE<"alcgr", 0xB988, z_addcarry, GR64, GR64>; 1034 1035 // Addition of memory. 1036 def ALC : BinaryRXY<"alc", 0xE398, z_addcarry, GR32, load, 4>; 1037 def ALCG : BinaryRXY<"alcg", 0xE388, z_addcarry, GR64, load, 8>; 1038} 1039 1040// Addition that does not modify the condition code. 1041def ALSIHN : BinaryRIL<"alsihn", 0xCCB, null_frag, GRH32, simm32>, 1042 Requires<[FeatureHighWord]>; 1043 1044 1045//===----------------------------------------------------------------------===// 1046// Subtraction 1047//===----------------------------------------------------------------------===// 1048 1049// Subtraction producing a signed overflow flag. 1050let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8, 1051 CCIfNoSignedWrap = 1 in { 1052 // Subtraction of a register. 1053 defm SR : BinaryRRAndK<"sr", 0x1B, 0xB9F9, z_ssub, GR32, GR32>; 1054 def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>; 1055 defm SGR : BinaryRREAndK<"sgr", 0xB909, 0xB9E9, z_ssub, GR64, GR64>; 1056 1057 // Subtraction from a high register. 1058 def SHHHR : BinaryRRFa<"shhhr", 0xB9C9, null_frag, GRH32, GRH32, GRH32>, 1059 Requires<[FeatureHighWord]>; 1060 def SHHLR : BinaryRRFa<"shhlr", 0xB9D9, null_frag, GRH32, GRH32, GR32>, 1061 Requires<[FeatureHighWord]>; 1062 1063 // Subtraction of memory. 1064 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, z_ssub, GR32, asextloadi16, 2>; 1065 defm S : BinaryRXPairAndPseudo<"s", 0x5B, 0xE35B, z_ssub, GR32, load, 4>; 1066 def SGH : BinaryRXY<"sgh", 0xE339, z_ssub, GR64, asextloadi16, 2>, 1067 Requires<[FeatureMiscellaneousExtensions2]>; 1068 def SGF : BinaryRXY<"sgf", 0xE319, z_ssub, GR64, asextloadi32, 4>; 1069 defm SG : BinaryRXYAndPseudo<"sg", 0xE309, z_ssub, GR64, load, 8>; 1070} 1071defm : SXB<z_ssub, GR64, SGFR>; 1072 1073// Subtracting an immediate is the same as adding the negated immediate. 1074let AddedComplexity = 1 in { 1075 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1076 (AHIMux GR32:$src1, imm32sx16n:$src2)>, 1077 Requires<[FeatureHighWord]>; 1078 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1079 (AFIMux GR32:$src1, simm32n:$src2)>, 1080 Requires<[FeatureHighWord]>; 1081 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1082 (AHI GR32:$src1, imm32sx16n:$src2)>; 1083 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1084 (AFI GR32:$src1, simm32n:$src2)>; 1085 def : Pat<(z_ssub GR64:$src1, imm64sx16n:$src2), 1086 (AGHI GR64:$src1, imm64sx16n:$src2)>; 1087 def : Pat<(z_ssub GR64:$src1, imm64sx32n:$src2), 1088 (AGFI GR64:$src1, imm64sx32n:$src2)>; 1089} 1090 1091// And vice versa in one special case, where we need to load a 1092// constant into a register in any case, but the negated constant 1093// requires fewer instructions to load. 1094def : Pat<(z_saddo GR64:$src1, imm64lh16n:$src2), 1095 (SGR GR64:$src1, (LLILH imm64lh16n:$src2))>; 1096def : Pat<(z_saddo GR64:$src1, imm64lf32n:$src2), 1097 (SGR GR64:$src1, (LLILF imm64lf32n:$src2))>; 1098 1099// Subtraction producing a carry. 1100let Defs = [CC], CCValues = 0x7, IsLogical = 1 in { 1101 // Subtraction of a register. 1102 defm SLR : BinaryRRAndK<"slr", 0x1F, 0xB9FB, z_usub, GR32, GR32>; 1103 def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>; 1104 defm SLGR : BinaryRREAndK<"slgr", 0xB90B, 0xB9EB, z_usub, GR64, GR64>; 1105 1106 // Subtraction from a high register. 1107 def SLHHHR : BinaryRRFa<"slhhhr", 0xB9CB, null_frag, GRH32, GRH32, GRH32>, 1108 Requires<[FeatureHighWord]>; 1109 def SLHHLR : BinaryRRFa<"slhhlr", 0xB9DB, null_frag, GRH32, GRH32, GR32>, 1110 Requires<[FeatureHighWord]>; 1111 1112 // Subtraction of unsigned 32-bit immediates. 1113 def SLFI : BinaryRIL<"slfi", 0xC25, z_usub, GR32, uimm32>; 1114 def SLGFI : BinaryRIL<"slgfi", 0xC24, z_usub, GR64, imm64zx32>; 1115 1116 // Subtraction of memory. 1117 defm SL : BinaryRXPairAndPseudo<"sl", 0x5F, 0xE35F, z_usub, GR32, load, 4>; 1118 def SLGF : BinaryRXY<"slgf", 0xE31B, z_usub, GR64, azextloadi32, 4>; 1119 defm SLG : BinaryRXYAndPseudo<"slg", 0xE30B, z_usub, GR64, load, 8>; 1120} 1121defm : ZXB<z_usub, GR64, SLGFR>; 1122 1123// Subtracting an immediate is the same as adding the negated immediate. 1124let AddedComplexity = 1 in { 1125 def : Pat<(z_usub GR32:$src1, imm32sx16n:$src2), 1126 (ALHSIK GR32:$src1, imm32sx16n:$src2)>, 1127 Requires<[FeatureDistinctOps]>; 1128 def : Pat<(z_usub GR64:$src1, imm64sx16n:$src2), 1129 (ALGHSIK GR64:$src1, imm64sx16n:$src2)>, 1130 Requires<[FeatureDistinctOps]>; 1131} 1132 1133// And vice versa in one special case (but we prefer addition). 1134def : Pat<(add GR64:$src1, imm64zx32n:$src2), 1135 (SLGFI GR64:$src1, imm64zx32n:$src2)>; 1136 1137// Subtraction producing and using a carry. 1138let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in { 1139 // Subtraction of a register. 1140 def SLBR : BinaryRRE<"slbr", 0xB999, z_subcarry, GR32, GR32>; 1141 def SLBGR : BinaryRRE<"slbgr", 0xB989, z_subcarry, GR64, GR64>; 1142 1143 // Subtraction of memory. 1144 def SLB : BinaryRXY<"slb", 0xE399, z_subcarry, GR32, load, 4>; 1145 def SLBG : BinaryRXY<"slbg", 0xE389, z_subcarry, GR64, load, 8>; 1146} 1147 1148 1149//===----------------------------------------------------------------------===// 1150// AND 1151//===----------------------------------------------------------------------===// 1152 1153let Defs = [CC] in { 1154 // ANDs of a register. 1155 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1156 defm NR : BinaryRRAndK<"nr", 0x14, 0xB9F4, and, GR32, GR32>; 1157 defm NGR : BinaryRREAndK<"ngr", 0xB980, 0xB9E4, and, GR64, GR64>; 1158 } 1159 1160 let isConvertibleToThreeAddress = 1 in { 1161 // ANDs of a 16-bit immediate, leaving other bits unaffected. 1162 // The CC result only reflects the 16-bit field, not the full register. 1163 // 1164 // NIxMux expands to NI[LH]x, depending on the choice of register. 1165 def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>, 1166 Requires<[FeatureHighWord]>; 1167 def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>, 1168 Requires<[FeatureHighWord]>; 1169 def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; 1170 def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; 1171 def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>; 1172 def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>; 1173 def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>; 1174 def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>; 1175 def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>; 1176 def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>; 1177 1178 // ANDs of a 32-bit immediate, leaving other bits unaffected. 1179 // The CC result only reflects the 32-bit field, which means we can 1180 // use it as a zero indicator for i32 operations but not otherwise. 1181 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1182 // Expands to NILF or NIHF, depending on the choice of register. 1183 def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>, 1184 Requires<[FeatureHighWord]>; 1185 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; 1186 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>; 1187 } 1188 def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>; 1189 def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>; 1190 } 1191 1192 // ANDs of memory. 1193 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1194 defm N : BinaryRXPairAndPseudo<"n", 0x54, 0xE354, and, GR32, load, 4>; 1195 defm NG : BinaryRXYAndPseudo<"ng", 0xE380, and, GR64, load, 8>; 1196 } 1197 1198 // AND to memory 1199 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>; 1200 1201 // Block AND. 1202 let mayLoad = 1, mayStore = 1 in 1203 defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>; 1204} 1205defm : RMWIByte<and, bdaddr12pair, NI>; 1206defm : RMWIByte<and, bdaddr20pair, NIY>; 1207 1208//===----------------------------------------------------------------------===// 1209// OR 1210//===----------------------------------------------------------------------===// 1211 1212let Defs = [CC] in { 1213 // ORs of a register. 1214 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1215 defm OR : BinaryRRAndK<"or", 0x16, 0xB9F6, or, GR32, GR32>; 1216 defm OGR : BinaryRREAndK<"ogr", 0xB981, 0xB9E6, or, GR64, GR64>; 1217 } 1218 1219 // ORs of a 16-bit immediate, leaving other bits unaffected. 1220 // The CC result only reflects the 16-bit field, not the full register. 1221 // 1222 // OIxMux expands to OI[LH]x, depending on the choice of register. 1223 def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>, 1224 Requires<[FeatureHighWord]>; 1225 def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>, 1226 Requires<[FeatureHighWord]>; 1227 def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; 1228 def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; 1229 def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>; 1230 def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>; 1231 def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>; 1232 def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>; 1233 def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>; 1234 def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>; 1235 1236 // ORs of a 32-bit immediate, leaving other bits unaffected. 1237 // The CC result only reflects the 32-bit field, which means we can 1238 // use it as a zero indicator for i32 operations but not otherwise. 1239 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1240 // Expands to OILF or OIHF, depending on the choice of register. 1241 def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>, 1242 Requires<[FeatureHighWord]>; 1243 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; 1244 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>; 1245 } 1246 def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>; 1247 def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>; 1248 1249 // ORs of memory. 1250 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1251 defm O : BinaryRXPairAndPseudo<"o", 0x56, 0xE356, or, GR32, load, 4>; 1252 defm OG : BinaryRXYAndPseudo<"og", 0xE381, or, GR64, load, 8>; 1253 } 1254 1255 // OR to memory 1256 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>; 1257 1258 // Block OR. 1259 let mayLoad = 1, mayStore = 1 in 1260 defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>; 1261} 1262defm : RMWIByte<or, bdaddr12pair, OI>; 1263defm : RMWIByte<or, bdaddr20pair, OIY>; 1264 1265//===----------------------------------------------------------------------===// 1266// XOR 1267//===----------------------------------------------------------------------===// 1268 1269let Defs = [CC] in { 1270 // XORs of a register. 1271 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1272 defm XR : BinaryRRAndK<"xr", 0x17, 0xB9F7, xor, GR32, GR32>; 1273 defm XGR : BinaryRREAndK<"xgr", 0xB982, 0xB9E7, xor, GR64, GR64>; 1274 } 1275 1276 // XORs of a 32-bit immediate, leaving other bits unaffected. 1277 // The CC result only reflects the 32-bit field, which means we can 1278 // use it as a zero indicator for i32 operations but not otherwise. 1279 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1280 // Expands to XILF or XIHF, depending on the choice of register. 1281 def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>, 1282 Requires<[FeatureHighWord]>; 1283 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; 1284 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>; 1285 } 1286 def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>; 1287 def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>; 1288 1289 // XORs of memory. 1290 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1291 defm X : BinaryRXPairAndPseudo<"x",0x57, 0xE357, xor, GR32, load, 4>; 1292 defm XG : BinaryRXYAndPseudo<"xg", 0xE382, xor, GR64, load, 8>; 1293 } 1294 1295 // XOR to memory 1296 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>; 1297 1298 // Block XOR. 1299 let mayLoad = 1, mayStore = 1 in 1300 defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>; 1301} 1302defm : RMWIByte<xor, bdaddr12pair, XI>; 1303defm : RMWIByte<xor, bdaddr20pair, XIY>; 1304 1305//===----------------------------------------------------------------------===// 1306// Combined logical operations 1307//===----------------------------------------------------------------------===// 1308 1309let Predicates = [FeatureMiscellaneousExtensions3], 1310 Defs = [CC] in { 1311 // AND with complement. 1312 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1313 def NCRK : BinaryRRFa<"ncrk", 0xB9F5, andc, GR32, GR32, GR32>; 1314 def NCGRK : BinaryRRFa<"ncgrk", 0xB9E5, andc, GR64, GR64, GR64>; 1315 } 1316 1317 // OR with complement. 1318 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1319 def OCRK : BinaryRRFa<"ocrk", 0xB975, orc, GR32, GR32, GR32>; 1320 def OCGRK : BinaryRRFa<"ocgrk", 0xB965, orc, GR64, GR64, GR64>; 1321 } 1322 1323 // NAND. 1324 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1325 def NNRK : BinaryRRFa<"nnrk", 0xB974, nand, GR32, GR32, GR32>; 1326 def NNGRK : BinaryRRFa<"nngrk", 0xB964, nand, GR64, GR64, GR64>; 1327 } 1328 1329 // NOR. 1330 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1331 def NORK : BinaryRRFa<"nork", 0xB976, nor, GR32, GR32, GR32>; 1332 def NOGRK : BinaryRRFa<"nogrk", 0xB966, nor, GR64, GR64, GR64>; 1333 } 1334 1335 // NXOR. 1336 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1337 def NXRK : BinaryRRFa<"nxrk", 0xB977, nxor, GR32, GR32, GR32>; 1338 def NXGRK : BinaryRRFa<"nxgrk", 0xB967, nxor, GR64, GR64, GR64>; 1339 } 1340} 1341 1342//===----------------------------------------------------------------------===// 1343// Multiplication 1344//===----------------------------------------------------------------------===// 1345 1346// Multiplication of a register, setting the condition code. We prefer these 1347// over MS(G)R if available, even though we cannot use the condition code, 1348// since they are three-operand instructions. 1349let Predicates = [FeatureMiscellaneousExtensions2], 1350 Defs = [CC], isCommutable = 1 in { 1351 def MSRKC : BinaryRRFa<"msrkc", 0xB9FD, mul, GR32, GR32, GR32>; 1352 def MSGRKC : BinaryRRFa<"msgrkc", 0xB9ED, mul, GR64, GR64, GR64>; 1353} 1354 1355// Multiplication of a register. 1356let isCommutable = 1 in { 1357 def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>; 1358 def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>; 1359} 1360def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>; 1361defm : SXB<mul, GR64, MSGFR>; 1362 1363// Multiplication of a signed 16-bit immediate. 1364def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>; 1365def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>; 1366 1367// Multiplication of a signed 32-bit immediate. 1368def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>; 1369def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; 1370 1371// Multiplication of memory. 1372defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>; 1373defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>; 1374def MGH : BinaryRXY<"mgh", 0xE33C, mul, GR64, asextloadi16, 2>, 1375 Requires<[FeatureMiscellaneousExtensions2]>; 1376def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>; 1377def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>; 1378 1379// Multiplication of memory, setting the condition code. 1380let Predicates = [FeatureMiscellaneousExtensions2], Defs = [CC] in { 1381 defm MSC : BinaryRXYAndPseudo<"msc", 0xE353, null_frag, GR32, load, 4>; 1382 defm MSGC : BinaryRXYAndPseudo<"msgc", 0xE383, null_frag, GR64, load, 8>; 1383} 1384 1385// Multiplication of a register, producing two results. 1386def MR : BinaryRR <"mr", 0x1C, null_frag, GR128, GR32>; 1387def MGRK : BinaryRRFa<"mgrk", 0xB9EC, null_frag, GR128, GR64, GR64>, 1388 Requires<[FeatureMiscellaneousExtensions2]>; 1389def MLR : BinaryRRE<"mlr", 0xB996, null_frag, GR128, GR32>; 1390def MLGR : BinaryRRE<"mlgr", 0xB986, null_frag, GR128, GR64>; 1391 1392def : Pat<(z_smul_lohi GR64:$src1, GR64:$src2), 1393 (MGRK GR64:$src1, GR64:$src2)>; 1394def : Pat<(z_umul_lohi GR64:$src1, GR64:$src2), 1395 (MLGR (AEXT128 GR64:$src1), GR64:$src2)>; 1396 1397// Multiplication of memory, producing two results. 1398def M : BinaryRX <"m", 0x5C, null_frag, GR128, load, 4>; 1399def MFY : BinaryRXY<"mfy", 0xE35C, null_frag, GR128, load, 4>; 1400def MG : BinaryRXY<"mg", 0xE384, null_frag, GR128, load, 8>, 1401 Requires<[FeatureMiscellaneousExtensions2]>; 1402def ML : BinaryRXY<"ml", 0xE396, null_frag, GR128, load, 4>; 1403def MLG : BinaryRXY<"mlg", 0xE386, null_frag, GR128, load, 8>; 1404 1405def : Pat<(z_smul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1406 (MG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1407def : Pat<(z_umul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1408 (MLG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1409 1410//===----------------------------------------------------------------------===// 1411// Division and remainder 1412//===----------------------------------------------------------------------===// 1413 1414let hasSideEffects = 1 in { // Do not speculatively execute. 1415 // Division and remainder, from registers. 1416 def DR : BinaryRR <"dr", 0x1D, null_frag, GR128, GR32>; 1417 def DSGFR : BinaryRRE<"dsgfr", 0xB91D, null_frag, GR128, GR32>; 1418 def DSGR : BinaryRRE<"dsgr", 0xB90D, null_frag, GR128, GR64>; 1419 def DLR : BinaryRRE<"dlr", 0xB997, null_frag, GR128, GR32>; 1420 def DLGR : BinaryRRE<"dlgr", 0xB987, null_frag, GR128, GR64>; 1421 1422 // Division and remainder, from memory. 1423 def D : BinaryRX <"d", 0x5D, null_frag, GR128, load, 4>; 1424 def DSGF : BinaryRXY<"dsgf", 0xE31D, null_frag, GR128, load, 4>; 1425 def DSG : BinaryRXY<"dsg", 0xE30D, null_frag, GR128, load, 8>; 1426 def DL : BinaryRXY<"dl", 0xE397, null_frag, GR128, load, 4>; 1427 def DLG : BinaryRXY<"dlg", 0xE387, null_frag, GR128, load, 8>; 1428} 1429def : Pat<(z_sdivrem GR64:$src1, GR32:$src2), 1430 (DSGFR (AEXT128 GR64:$src1), GR32:$src2)>; 1431def : Pat<(z_sdivrem GR64:$src1, (i32 (load bdxaddr20only:$src2))), 1432 (DSGF (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1433def : Pat<(z_sdivrem GR64:$src1, GR64:$src2), 1434 (DSGR (AEXT128 GR64:$src1), GR64:$src2)>; 1435def : Pat<(z_sdivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1436 (DSG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1437 1438def : Pat<(z_udivrem GR32:$src1, GR32:$src2), 1439 (DLR (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1440 subreg_l32)), GR32:$src2)>; 1441def : Pat<(z_udivrem GR32:$src1, (i32 (load bdxaddr20only:$src2))), 1442 (DL (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1443 subreg_l32)), bdxaddr20only:$src2)>; 1444def : Pat<(z_udivrem GR64:$src1, GR64:$src2), 1445 (DLGR (ZEXT128 GR64:$src1), GR64:$src2)>; 1446def : Pat<(z_udivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1447 (DLG (ZEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1448 1449//===----------------------------------------------------------------------===// 1450// Shifts 1451//===----------------------------------------------------------------------===// 1452 1453// Logical shift left. 1454defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shiftop<shl>, GR32>; 1455def SLLG : BinaryRSY<"sllg", 0xEB0D, shiftop<shl>, GR64>; 1456def SLDL : BinaryRS<"sldl", 0x8D, null_frag, GR128>; 1457 1458// Arithmetic shift left. 1459let Defs = [CC] in { 1460 defm SLA : BinaryRSAndK<"sla", 0x8B, 0xEBDD, null_frag, GR32>; 1461 def SLAG : BinaryRSY<"slag", 0xEB0B, null_frag, GR64>; 1462 def SLDA : BinaryRS<"slda", 0x8F, null_frag, GR128>; 1463} 1464 1465// Logical shift right. 1466defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, shiftop<srl>, GR32>; 1467def SRLG : BinaryRSY<"srlg", 0xEB0C, shiftop<srl>, GR64>; 1468def SRDL : BinaryRS<"srdl", 0x8C, null_frag, GR128>; 1469 1470// Arithmetic shift right. 1471let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 1472 defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, shiftop<sra>, GR32>; 1473 def SRAG : BinaryRSY<"srag", 0xEB0A, shiftop<sra>, GR64>; 1474 def SRDA : BinaryRS<"srda", 0x8E, null_frag, GR128>; 1475} 1476 1477// Rotate left. 1478def RLL : BinaryRSY<"rll", 0xEB1D, shiftop<rotl>, GR32>; 1479def RLLG : BinaryRSY<"rllg", 0xEB1C, shiftop<rotl>, GR64>; 1480 1481// Rotate second operand left and inserted selected bits into first operand. 1482// These can act like 32-bit operands provided that the constant start and 1483// end bits (operands 2 and 3) are in the range [32, 64). 1484let Defs = [CC] in { 1485 let isCodeGenOnly = 1 in 1486 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; 1487 let CCValues = 0xE, CompareZeroCCMask = 0xE in 1488 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; 1489} 1490 1491// On zEC12 we have a variant of RISBG that does not set CC. 1492let Predicates = [FeatureMiscellaneousExtensions] in 1493 def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>; 1494 1495// Forms of RISBG that only affect one word of the destination register. 1496// They do not set CC. 1497let Predicates = [FeatureHighWord] in { 1498 def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>; 1499 def RISBLL : RotateSelectAliasRIEf<GR32, GR32>; 1500 def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>; 1501 def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>; 1502 def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>; 1503 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>; 1504 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>; 1505} 1506 1507// Rotate second operand left and perform a logical operation with selected 1508// bits of the first operand. The CC result only describes the selected bits, 1509// so isn't useful for a full comparison against zero. 1510let Defs = [CC] in { 1511 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>; 1512 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>; 1513 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>; 1514} 1515 1516//===----------------------------------------------------------------------===// 1517// Comparison 1518//===----------------------------------------------------------------------===// 1519 1520// Signed comparisons. We put these before the unsigned comparisons because 1521// some of the signed forms have COMPARE AND BRANCH equivalents whereas none 1522// of the unsigned forms do. 1523let Defs = [CC], CCValues = 0xE in { 1524 // Comparison with a register. 1525 def CR : CompareRR <"cr", 0x19, z_scmp, GR32, GR32>; 1526 def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>; 1527 def CGR : CompareRRE<"cgr", 0xB920, z_scmp, GR64, GR64>; 1528 1529 // Comparison with a high register. 1530 def CHHR : CompareRRE<"chhr", 0xB9CD, null_frag, GRH32, GRH32>, 1531 Requires<[FeatureHighWord]>; 1532 def CHLR : CompareRRE<"chlr", 0xB9DD, null_frag, GRH32, GR32>, 1533 Requires<[FeatureHighWord]>; 1534 1535 // Comparison with a signed 16-bit immediate. CHIMux expands to CHI or CIH, 1536 // depending on the choice of register. 1537 def CHIMux : CompareRIPseudo<z_scmp, GRX32, imm32sx16>, 1538 Requires<[FeatureHighWord]>; 1539 def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>; 1540 def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>; 1541 1542 // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH, 1543 // depending on the choice of register. 1544 def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>, 1545 Requires<[FeatureHighWord]>; 1546 def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>; 1547 def CIH : CompareRIL<"cih", 0xCCD, z_scmp, GRH32, simm32>, 1548 Requires<[FeatureHighWord]>; 1549 def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>; 1550 1551 // Comparison with memory. 1552 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>; 1553 def CMux : CompareRXYPseudo<z_scmp, GRX32, load, 4>, 1554 Requires<[FeatureHighWord]>; 1555 defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, load, 4>; 1556 def CHF : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>, 1557 Requires<[FeatureHighWord]>; 1558 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>; 1559 def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>; 1560 def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, load, 8>; 1561 def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_asextloadi16>; 1562 def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_load>; 1563 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>; 1564 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>; 1565 def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_load>; 1566 1567 // Comparison between memory and a signed 16-bit immediate. 1568 def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>; 1569 def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, load, imm32sx16>; 1570 def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>; 1571} 1572defm : SXB<z_scmp, GR64, CGFR>; 1573 1574// Unsigned comparisons. 1575let Defs = [CC], CCValues = 0xE, IsLogical = 1 in { 1576 // Comparison with a register. 1577 def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>; 1578 def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>; 1579 def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>; 1580 1581 // Comparison with a high register. 1582 def CLHHR : CompareRRE<"clhhr", 0xB9CF, null_frag, GRH32, GRH32>, 1583 Requires<[FeatureHighWord]>; 1584 def CLHLR : CompareRRE<"clhlr", 0xB9DF, null_frag, GRH32, GR32>, 1585 Requires<[FeatureHighWord]>; 1586 1587 // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI 1588 // or CLIH, depending on the choice of register. 1589 def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>, 1590 Requires<[FeatureHighWord]>; 1591 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>; 1592 def CLIH : CompareRIL<"clih", 0xCCF, z_ucmp, GRH32, uimm32>, 1593 Requires<[FeatureHighWord]>; 1594 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>; 1595 1596 // Comparison with memory. 1597 def CLMux : CompareRXYPseudo<z_ucmp, GRX32, load, 4>, 1598 Requires<[FeatureHighWord]>; 1599 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>; 1600 def CLHF : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>, 1601 Requires<[FeatureHighWord]>; 1602 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>; 1603 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>; 1604 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32, 1605 aligned_azextloadi16>; 1606 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32, 1607 aligned_load>; 1608 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64, 1609 aligned_azextloadi16>; 1610 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64, 1611 aligned_azextloadi32>; 1612 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64, 1613 aligned_load>; 1614 1615 // Comparison between memory and an unsigned 8-bit immediate. 1616 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>; 1617 1618 // Comparison between memory and an unsigned 16-bit immediate. 1619 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>; 1620 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>; 1621 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>; 1622} 1623defm : ZXB<z_ucmp, GR64, CLGFR>; 1624 1625// Memory-to-memory comparison. 1626let mayLoad = 1, Defs = [CC] in { 1627 defm CLC : CompareMemorySS<"clc", 0xD5, z_clc, z_clc_loop>; 1628 def CLCL : SideEffectBinaryMemMemRR<"clcl", 0x0F, GR128, GR128>; 1629 def CLCLE : SideEffectTernaryMemMemRS<"clcle", 0xA9, GR128, GR128>; 1630 def CLCLU : SideEffectTernaryMemMemRSY<"clclu", 0xEB8F, GR128, GR128>; 1631} 1632 1633// String comparison. 1634let mayLoad = 1, Defs = [CC] in 1635 defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>; 1636 1637// Test under mask. 1638let Defs = [CC] in { 1639 // TMxMux expands to TM[LH]x, depending on the choice of register. 1640 def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>, 1641 Requires<[FeatureHighWord]>; 1642 def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>, 1643 Requires<[FeatureHighWord]>; 1644 def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>; 1645 def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>; 1646 def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>; 1647 def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>; 1648 1649 def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>; 1650 def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>; 1651 def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>; 1652 def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>; 1653 1654 defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>; 1655} 1656 1657def TML : InstAlias<"tml\t$R, $I", (TMLL GR32:$R, imm32ll16:$I), 0>; 1658def TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>; 1659 1660// Compare logical characters under mask -- not (yet) used for codegen. 1661let Defs = [CC] in { 1662 defm CLM : CompareRSPair<"clm", 0xBD, 0xEB21, GR32, 0>; 1663 def CLMH : CompareRSY<"clmh", 0xEB20, GRH32, 0>; 1664} 1665 1666//===----------------------------------------------------------------------===// 1667// Prefetch and execution hint 1668//===----------------------------------------------------------------------===// 1669 1670let mayLoad = 1, mayStore = 1 in { 1671 def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>; 1672 def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>; 1673} 1674 1675let Predicates = [FeatureExecutionHint], hasSideEffects = 1 in { 1676 // Branch Prediction Preload 1677 def BPP : BranchPreloadSMI<"bpp", 0xC7>; 1678 def BPRP : BranchPreloadMII<"bprp", 0xC5>; 1679 1680 // Next Instruction Access Intent 1681 def NIAI : SideEffectBinaryIE<"niai", 0xB2FA, imm32zx4, imm32zx4>; 1682} 1683 1684//===----------------------------------------------------------------------===// 1685// Atomic operations 1686//===----------------------------------------------------------------------===// 1687 1688// A serialization instruction that acts as a barrier for all memory 1689// accesses, which expands to "bcr 14, 0". 1690let hasSideEffects = 1 in 1691def Serialize : Alias<2, (outs), (ins), []>; 1692 1693// A pseudo instruction that serves as a compiler barrier. 1694let hasSideEffects = 1, hasNoSchedulingInfo = 1 in 1695def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>; 1696 1697let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1698 def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_32, GR32>; 1699 def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_64, GR64>; 1700 def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>; 1701 def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>; 1702 def LAN : LoadAndOpRSY<"lan", 0xEBF4, atomic_load_and_32, GR32>; 1703 def LANG : LoadAndOpRSY<"lang", 0xEBE4, atomic_load_and_64, GR64>; 1704 def LAO : LoadAndOpRSY<"lao", 0xEBF6, atomic_load_or_32, GR32>; 1705 def LAOG : LoadAndOpRSY<"laog", 0xEBE6, atomic_load_or_64, GR64>; 1706 def LAX : LoadAndOpRSY<"lax", 0xEBF7, atomic_load_xor_32, GR32>; 1707 def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, atomic_load_xor_64, GR64>; 1708} 1709 1710def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; 1711def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>; 1712def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>; 1713 1714def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>; 1715def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>; 1716let Predicates = [FeatureNoInterlockedAccess1] in { 1717 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>; 1718 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>; 1719 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>; 1720 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>; 1721 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>; 1722 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>; 1723} 1724 1725def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>; 1726def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>; 1727def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>; 1728 1729def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>; 1730def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>; 1731let Predicates = [FeatureNoInterlockedAccess1] in { 1732 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>; 1733 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm32<atomic_load_and_32, 1734 imm32ll16c>; 1735 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm32<atomic_load_and_32, 1736 imm32lh16c>; 1737 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>; 1738 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>; 1739 def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1740 imm64ll16c>; 1741 def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1742 imm64lh16c>; 1743 def ATOMIC_LOAD_NIHL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1744 imm64hl16c>; 1745 def ATOMIC_LOAD_NIHH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1746 imm64hh16c>; 1747 def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1748 imm64lf32c>; 1749 def ATOMIC_LOAD_NIHF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1750 imm64hf32c>; 1751} 1752 1753def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>; 1754def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>; 1755let Predicates = [FeatureNoInterlockedAccess1] in { 1756 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>; 1757 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>; 1758 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>; 1759 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>; 1760 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>; 1761 def ATOMIC_LOAD_OILL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>; 1762 def ATOMIC_LOAD_OILH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>; 1763 def ATOMIC_LOAD_OIHL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>; 1764 def ATOMIC_LOAD_OIHH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>; 1765 def ATOMIC_LOAD_OILF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>; 1766 def ATOMIC_LOAD_OIHF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>; 1767} 1768 1769def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>; 1770def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>; 1771let Predicates = [FeatureNoInterlockedAccess1] in { 1772 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>; 1773 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>; 1774 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>; 1775 def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>; 1776 def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>; 1777} 1778 1779def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; 1780def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, 1781 imm32lh16c>; 1782def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>; 1783def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1784 imm32ll16c>; 1785def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1786 imm32lh16c>; 1787def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>; 1788def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>; 1789def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1790 imm64ll16c>; 1791def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1792 imm64lh16c>; 1793def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1794 imm64hl16c>; 1795def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1796 imm64hh16c>; 1797def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1798 imm64lf32c>; 1799def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1800 imm64hf32c>; 1801 1802def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>; 1803def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>; 1804def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>; 1805 1806def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>; 1807def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>; 1808def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>; 1809 1810def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>; 1811def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>; 1812def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>; 1813 1814def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>; 1815def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>; 1816def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>; 1817 1818def ATOMIC_CMP_SWAPW 1819 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1820 ADDR32:$bitshift, ADDR32:$negbitshift, 1821 uimm32:$bitsize), 1822 [(set GR32:$dst, 1823 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1824 ADDR32:$bitshift, ADDR32:$negbitshift, 1825 uimm32:$bitsize))]> { 1826 let Defs = [CC]; 1827 let mayLoad = 1; 1828 let mayStore = 1; 1829 let usesCustomInserter = 1; 1830 let hasNoSchedulingInfo = 1; 1831} 1832 1833// Test and set. 1834let mayLoad = 1, Defs = [CC] in 1835 def TS : StoreInherentS<"ts", 0x9300, null_frag, 1>; 1836 1837// Compare and swap. 1838let Defs = [CC] in { 1839 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, z_atomic_cmp_swap, GR32>; 1840 def CSG : CmpSwapRSY<"csg", 0xEB30, z_atomic_cmp_swap, GR64>; 1841} 1842 1843// Compare double and swap. 1844let Defs = [CC] in { 1845 defm CDS : CmpSwapRSPair<"cds", 0xBB, 0xEB31, null_frag, GR128>; 1846 def CDSG : CmpSwapRSY<"cdsg", 0xEB3E, z_atomic_cmp_swap_128, GR128>; 1847} 1848 1849// Compare and swap and store. 1850let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad = 1 in 1851 def CSST : SideEffectTernarySSF<"csst", 0xC82, GR64>; 1852 1853// Perform locked operation. 1854let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad =1 in 1855 def PLO : SideEffectQuaternarySSe<"plo", 0xEE, GR64>; 1856 1857// Load/store pair from/to quadword. 1858def LPQ : UnaryRXY<"lpq", 0xE38F, z_atomic_load_128, GR128, 16>; 1859def STPQ : StoreRXY<"stpq", 0xE38E, z_atomic_store_128, GR128, 16>; 1860 1861// Load pair disjoint. 1862let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1863 def LPD : BinarySSF<"lpd", 0xC84, GR128>; 1864 def LPDG : BinarySSF<"lpdg", 0xC85, GR128>; 1865} 1866 1867//===----------------------------------------------------------------------===// 1868// Translate and convert 1869//===----------------------------------------------------------------------===// 1870 1871let mayLoad = 1, mayStore = 1 in 1872 def TR : SideEffectBinarySSa<"tr", 0xDC>; 1873 1874let mayLoad = 1, Defs = [CC, R0L, R1D] in { 1875 def TRT : SideEffectBinarySSa<"trt", 0xDD>; 1876 def TRTR : SideEffectBinarySSa<"trtr", 0xD0>; 1877} 1878 1879let mayLoad = 1, mayStore = 1, Uses = [R0L] in 1880 def TRE : SideEffectBinaryMemMemRRE<"tre", 0xB2A5, GR128, GR64>; 1881 1882let mayLoad = 1, Uses = [R1D], Defs = [CC] in { 1883 defm TRTE : BinaryMemRRFcOpt<"trte", 0xB9BF, GR128, GR64>; 1884 defm TRTRE : BinaryMemRRFcOpt<"trtre", 0xB9BD, GR128, GR64>; 1885} 1886 1887let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1888 defm TROO : SideEffectTernaryMemMemRRFcOpt<"troo", 0xB993, GR128, GR64>; 1889 defm TROT : SideEffectTernaryMemMemRRFcOpt<"trot", 0xB992, GR128, GR64>; 1890 defm TRTO : SideEffectTernaryMemMemRRFcOpt<"trto", 0xB991, GR128, GR64>; 1891 defm TRTT : SideEffectTernaryMemMemRRFcOpt<"trtt", 0xB990, GR128, GR64>; 1892} 1893 1894let mayLoad = 1, mayStore = 1, Defs = [CC] in { 1895 defm CU12 : SideEffectTernaryMemMemRRFcOpt<"cu12", 0xB2A7, GR128, GR128>; 1896 defm CU14 : SideEffectTernaryMemMemRRFcOpt<"cu14", 0xB9B0, GR128, GR128>; 1897 defm CU21 : SideEffectTernaryMemMemRRFcOpt<"cu21", 0xB2A6, GR128, GR128>; 1898 defm CU24 : SideEffectTernaryMemMemRRFcOpt<"cu24", 0xB9B1, GR128, GR128>; 1899 def CU41 : SideEffectBinaryMemMemRRE<"cu41", 0xB9B2, GR128, GR128>; 1900 def CU42 : SideEffectBinaryMemMemRRE<"cu42", 0xB9B3, GR128, GR128>; 1901 1902 let isAsmParserOnly = 1 in { 1903 defm CUUTF : SideEffectTernaryMemMemRRFcOpt<"cuutf", 0xB2A6, GR128, GR128>; 1904 defm CUTFU : SideEffectTernaryMemMemRRFcOpt<"cutfu", 0xB2A7, GR128, GR128>; 1905 } 1906} 1907 1908//===----------------------------------------------------------------------===// 1909// Message-security assist 1910//===----------------------------------------------------------------------===// 1911 1912let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1913 def KM : SideEffectBinaryMemMemRRE<"km", 0xB92E, GR128, GR128>; 1914 def KMC : SideEffectBinaryMemMemRRE<"kmc", 0xB92F, GR128, GR128>; 1915 1916 def KIMD : SideEffectBinaryMemRRE<"kimd", 0xB93E, GR64, GR128>; 1917 def KLMD : SideEffectBinaryMemRRE<"klmd", 0xB93F, GR64, GR128>; 1918 def KMAC : SideEffectBinaryMemRRE<"kmac", 0xB91E, GR64, GR128>; 1919 1920 let Predicates = [FeatureMessageSecurityAssist4] in { 1921 def KMF : SideEffectBinaryMemMemRRE<"kmf", 0xB92A, GR128, GR128>; 1922 def KMO : SideEffectBinaryMemMemRRE<"kmo", 0xB92B, GR128, GR128>; 1923 def KMCTR : SideEffectTernaryMemMemMemRRFb<"kmctr", 0xB92D, 1924 GR128, GR128, GR128>; 1925 def PCC : SideEffectInherentRRE<"pcc", 0xB92C>; 1926 } 1927 1928 let Predicates = [FeatureMessageSecurityAssist5] in 1929 def PPNO : SideEffectBinaryMemMemRRE<"ppno", 0xB93C, GR128, GR128>; 1930 let Predicates = [FeatureMessageSecurityAssist7], isAsmParserOnly = 1 in 1931 def PRNO : SideEffectBinaryMemMemRRE<"prno", 0xB93C, GR128, GR128>; 1932 1933 let Predicates = [FeatureMessageSecurityAssist8] in 1934 def KMA : SideEffectTernaryMemMemMemRRFb<"kma", 0xB929, 1935 GR128, GR128, GR128>; 1936 1937 let Predicates = [FeatureMessageSecurityAssist9] in 1938 def KDSA : SideEffectBinaryMemRRE<"kdsa", 0xB93A, GR64, GR128>; 1939} 1940 1941//===----------------------------------------------------------------------===// 1942// Guarded storage 1943//===----------------------------------------------------------------------===// 1944 1945// These instructions use and/or modify the guarded storage control 1946// registers, which we do not otherwise model, so they should have 1947// hasSideEffects. 1948let Predicates = [FeatureGuardedStorage], hasSideEffects = 1 in { 1949 def LGG : UnaryRXY<"lgg", 0xE34C, null_frag, GR64, 8>; 1950 def LLGFSG : UnaryRXY<"llgfsg", 0xE348, null_frag, GR64, 4>; 1951 1952 let mayLoad = 1 in 1953 def LGSC : SideEffectBinaryRXY<"lgsc", 0xE34D, GR64>; 1954 let mayStore = 1 in 1955 def STGSC : SideEffectBinaryRXY<"stgsc", 0xE349, GR64>; 1956} 1957 1958//===----------------------------------------------------------------------===// 1959// Decimal arithmetic 1960//===----------------------------------------------------------------------===// 1961 1962defm CVB : BinaryRXPair<"cvb",0x4F, 0xE306, null_frag, GR32, load, 4>; 1963def CVBG : BinaryRXY<"cvbg", 0xE30E, null_frag, GR64, load, 8>; 1964 1965defm CVD : StoreRXPair<"cvd", 0x4E, 0xE326, null_frag, GR32, 4>; 1966def CVDG : StoreRXY<"cvdg", 0xE32E, null_frag, GR64, 8>; 1967 1968let mayLoad = 1, mayStore = 1 in { 1969 def MVN : SideEffectBinarySSa<"mvn", 0xD1>; 1970 def MVZ : SideEffectBinarySSa<"mvz", 0xD3>; 1971 def MVO : SideEffectBinarySSb<"mvo", 0xF1>; 1972 1973 def PACK : SideEffectBinarySSb<"pack", 0xF2>; 1974 def PKA : SideEffectBinarySSf<"pka", 0xE9>; 1975 def PKU : SideEffectBinarySSf<"pku", 0xE1>; 1976 def UNPK : SideEffectBinarySSb<"unpk", 0xF3>; 1977 let Defs = [CC] in { 1978 def UNPKA : SideEffectBinarySSa<"unpka", 0xEA>; 1979 def UNPKU : SideEffectBinarySSa<"unpku", 0xE2>; 1980 } 1981} 1982 1983let mayLoad = 1, mayStore = 1 in { 1984 let Defs = [CC] in { 1985 def AP : SideEffectBinarySSb<"ap", 0xFA>; 1986 def SP : SideEffectBinarySSb<"sp", 0xFB>; 1987 def ZAP : SideEffectBinarySSb<"zap", 0xF8>; 1988 def SRP : SideEffectTernarySSc<"srp", 0xF0>; 1989 } 1990 def MP : SideEffectBinarySSb<"mp", 0xFC>; 1991 def DP : SideEffectBinarySSb<"dp", 0xFD>; 1992 let Defs = [CC] in { 1993 def ED : SideEffectBinarySSa<"ed", 0xDE>; 1994 def EDMK : SideEffectBinarySSa<"edmk", 0xDF>; 1995 } 1996} 1997 1998let Defs = [CC] in { 1999 def CP : CompareSSb<"cp", 0xF9>; 2000 def TP : TestRSL<"tp", 0xEBC0>; 2001} 2002 2003//===----------------------------------------------------------------------===// 2004// Access registers 2005//===----------------------------------------------------------------------===// 2006 2007// Read a 32-bit access register into a GR32. As with all GR32 operations, 2008// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful 2009// when a 64-bit address is stored in a pair of access registers. 2010def EAR : UnaryRRE<"ear", 0xB24F, null_frag, GR32, AR32>; 2011 2012// Set access register. 2013def SAR : UnaryRRE<"sar", 0xB24E, null_frag, AR32, GR32>; 2014 2015// Copy access register. 2016def CPYA : UnaryRRE<"cpya", 0xB24D, null_frag, AR32, AR32>; 2017 2018// Load address extended. 2019defm LAE : LoadAddressRXPair<"lae", 0x51, 0xE375, null_frag>; 2020 2021// Load access multiple. 2022defm LAM : LoadMultipleRSPair<"lam", 0x9A, 0xEB9A, AR32>; 2023 2024// Store access multiple. 2025defm STAM : StoreMultipleRSPair<"stam", 0x9B, 0xEB9B, AR32>; 2026 2027//===----------------------------------------------------------------------===// 2028// Program mask and addressing mode 2029//===----------------------------------------------------------------------===// 2030 2031// Extract CC and program mask into a register. CC ends up in bits 29 and 28. 2032let Uses = [CC] in 2033 def IPM : InherentRRE<"ipm", 0xB222, GR32, z_ipm>; 2034 2035// Set CC and program mask from a register. 2036let hasSideEffects = 1, Defs = [CC] in 2037 def SPM : SideEffectUnaryRR<"spm", 0x04, GR32>; 2038 2039// Branch and link - like BAS, but also extracts CC and program mask. 2040let isCall = 1, Uses = [CC], Defs = [CC] in { 2041 def BAL : CallRX<"bal", 0x45>; 2042 def BALR : CallRR<"balr", 0x05>; 2043} 2044 2045// Test addressing mode. 2046let Defs = [CC] in 2047 def TAM : SideEffectInherentE<"tam", 0x010B>; 2048 2049// Set addressing mode. 2050let hasSideEffects = 1 in { 2051 def SAM24 : SideEffectInherentE<"sam24", 0x010C>; 2052 def SAM31 : SideEffectInherentE<"sam31", 0x010D>; 2053 def SAM64 : SideEffectInherentE<"sam64", 0x010E>; 2054} 2055 2056// Branch and set mode. Not really a call, but also sets an output register. 2057let isBranch = 1, isTerminator = 1, isBarrier = 1 in 2058 def BSM : CallRR<"bsm", 0x0B>; 2059 2060// Branch and save and set mode. 2061let isCall = 1, Defs = [CC] in 2062 def BASSM : CallRR<"bassm", 0x0C>; 2063 2064//===----------------------------------------------------------------------===// 2065// Transactional execution 2066//===----------------------------------------------------------------------===// 2067 2068let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in { 2069 // Transaction Begin 2070 let mayStore = 1, usesCustomInserter = 1, Defs = [CC] in { 2071 def TBEGIN : TestBinarySIL<"tbegin", 0xE560, z_tbegin, imm32zx16>; 2072 let hasNoSchedulingInfo = 1 in 2073 def TBEGIN_nofloat : TestBinarySILPseudo<z_tbegin_nofloat, imm32zx16>; 2074 def TBEGINC : SideEffectBinarySIL<"tbeginc", 0xE561, 2075 int_s390_tbeginc, imm32zx16>; 2076 } 2077 2078 // Transaction End 2079 let Defs = [CC] in 2080 def TEND : TestInherentS<"tend", 0xB2F8, z_tend>; 2081 2082 // Transaction Abort 2083 let isTerminator = 1, isBarrier = 1, mayStore = 1, 2084 hasSideEffects = 1 in 2085 def TABORT : SideEffectAddressS<"tabort", 0xB2FC, int_s390_tabort>; 2086 2087 // Nontransactional Store 2088 def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; 2089 2090 // Extract Transaction Nesting Depth 2091 def ETND : InherentRRE<"etnd", 0xB2EC, GR32, int_s390_etnd>; 2092} 2093 2094//===----------------------------------------------------------------------===// 2095// Processor assist 2096//===----------------------------------------------------------------------===// 2097 2098let Predicates = [FeatureProcessorAssist] in { 2099 let hasSideEffects = 1 in 2100 def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>; 2101 def : Pat<(int_s390_ppa_txassist GR32:$src), 2102 (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 2103 zero_reg, 1)>; 2104} 2105 2106//===----------------------------------------------------------------------===// 2107// Miscellaneous Instructions. 2108//===----------------------------------------------------------------------===// 2109 2110// Find leftmost one, AKA count leading zeros. The instruction actually 2111// returns a pair of GR64s, the first giving the number of leading zeros 2112// and the second giving a copy of the source with the leftmost one bit 2113// cleared. We only use the first result here. 2114let Defs = [CC] in 2115 def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>; 2116def : Pat<(i64 (ctlz GR64:$src)), 2117 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>; 2118 2119// Population count. Counts bits set per byte or doubleword. 2120let Predicates = [FeatureMiscellaneousExtensions3] in { 2121 let Defs = [CC] in 2122 def POPCNTOpt : BinaryRRFc<"popcnt", 0xB9E1, GR64, GR64>; 2123 def : Pat<(ctpop GR64:$src), (POPCNTOpt GR64:$src, 8)>; 2124} 2125let Predicates = [FeaturePopulationCount], Defs = [CC] in 2126 def POPCNT : UnaryRRE<"popcnt", 0xB9E1, z_popcnt, GR64, GR64>; 2127 2128// Search a block of memory for a character. 2129let mayLoad = 1, Defs = [CC] in 2130 defm SRST : StringRRE<"srst", 0xB25E, z_search_string>; 2131let mayLoad = 1, Defs = [CC], Uses = [R0L] in 2132 def SRSTU : SideEffectBinaryMemMemRRE<"srstu", 0xB9BE, GR64, GR64>; 2133 2134// Compare until substring equal. 2135let mayLoad = 1, Defs = [CC], Uses = [R0L, R1L] in 2136 def CUSE : SideEffectBinaryMemMemRRE<"cuse", 0xB257, GR128, GR128>; 2137 2138// Compare and form codeword. 2139let mayLoad = 1, Defs = [CC, R1D, R2D, R3D], Uses = [R1D, R2D, R3D] in 2140 def CFC : SideEffectAddressS<"cfc", 0xB21A, null_frag>; 2141 2142// Update tree. 2143let mayLoad = 1, mayStore = 1, Defs = [CC, R0D, R1D, R2D, R3D, R5D], 2144 Uses = [R0D, R1D, R2D, R3D, R4D, R5D] in 2145 def UPT : SideEffectInherentE<"upt", 0x0102>; 2146 2147// Checksum. 2148let mayLoad = 1, Defs = [CC] in 2149 def CKSM : SideEffectBinaryMemMemRRE<"cksm", 0xB241, GR64, GR128>; 2150 2151// Compression call. 2152let mayLoad = 1, mayStore = 1, Defs = [CC, R1D], Uses = [R0L, R1D] in 2153 def CMPSC : SideEffectBinaryMemMemRRE<"cmpsc", 0xB263, GR128, GR128>; 2154 2155// Sort lists. 2156let Predicates = [FeatureEnhancedSort], 2157 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in 2158 def SORTL : SideEffectBinaryMemMemRRE<"sortl", 0xB938, GR128, GR128>; 2159 2160// Deflate conversion call. 2161let Predicates = [FeatureDeflateConversion], 2162 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in 2163 def DFLTCC : SideEffectTernaryMemMemRRFa<"dfltcc", 0xB939, 2164 GR128, GR128, GR64>; 2165 2166// NNPA. 2167let Predicates = [FeatureNNPAssist], 2168 mayLoad = 1, mayStore = 1, Defs = [R0D, CC], Uses = [R0D, R1D] in 2169 def NNPA : SideEffectInherentRRE<"nnpa", 0xB93B>; 2170 2171// Execute. 2172let hasSideEffects = 1 in { 2173 def EX : SideEffectBinaryRX<"ex", 0x44, ADDR64>; 2174 def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, ADDR64>; 2175 let hasNoSchedulingInfo = 1 in 2176 def EXRL_Pseudo : Alias<6, (outs), (ins i64imm:$TargetOpc, ADDR64:$lenMinus1, 2177 bdaddr12only:$bdl1, bdaddr12only:$bd2), 2178 []>; 2179} 2180 2181//===----------------------------------------------------------------------===// 2182// .insn directive instructions 2183//===----------------------------------------------------------------------===// 2184 2185let isCodeGenOnly = 1, hasSideEffects = 1 in { 2186 def InsnE : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>; 2187 def InsnRI : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2188 imm32sx16:$I2), 2189 ".insn ri,$enc,$R1,$I2", []>; 2190 def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2191 AnyReg:$R3, brtarget16:$I2), 2192 ".insn rie,$enc,$R1,$R3,$I2", []>; 2193 def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2194 brtarget32:$I2), 2195 ".insn ril,$enc,$R1,$I2", []>; 2196 def InsnRILU : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2197 uimm32:$I2), 2198 ".insn rilu,$enc,$R1,$I2", []>; 2199 def InsnRIS : DirectiveInsnRIS<(outs), 2200 (ins imm64zx48:$enc, AnyReg:$R1, 2201 imm32sx8:$I2, imm32zx4:$M3, 2202 bdaddr12only:$BD4), 2203 ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>; 2204 def InsnRR : DirectiveInsnRR<(outs), 2205 (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2), 2206 ".insn rr,$enc,$R1,$R2", []>; 2207 def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc, 2208 AnyReg:$R1, AnyReg:$R2), 2209 ".insn rre,$enc,$R1,$R2", []>; 2210 def InsnRRF : DirectiveInsnRRF<(outs), 2211 (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, 2212 AnyReg:$R3, imm32zx4:$M4), 2213 ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>; 2214 def InsnRRS : DirectiveInsnRRS<(outs), 2215 (ins imm64zx48:$enc, AnyReg:$R1, 2216 AnyReg:$R2, imm32zx4:$M3, 2217 bdaddr12only:$BD4), 2218 ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>; 2219 def InsnRS : DirectiveInsnRS<(outs), 2220 (ins imm64zx32:$enc, AnyReg:$R1, 2221 AnyReg:$R3, bdaddr12only:$BD2), 2222 ".insn rs,$enc,$R1,$R3,$BD2", []>; 2223 def InsnRSE : DirectiveInsnRSE<(outs), 2224 (ins imm64zx48:$enc, AnyReg:$R1, 2225 AnyReg:$R3, bdaddr12only:$BD2), 2226 ".insn rse,$enc,$R1,$R3,$BD2", []>; 2227 def InsnRSI : DirectiveInsnRSI<(outs), 2228 (ins imm64zx48:$enc, AnyReg:$R1, 2229 AnyReg:$R3, brtarget16:$RI2), 2230 ".insn rsi,$enc,$R1,$R3,$RI2", []>; 2231 def InsnRSY : DirectiveInsnRSY<(outs), 2232 (ins imm64zx48:$enc, AnyReg:$R1, 2233 AnyReg:$R3, bdaddr20only:$BD2), 2234 ".insn rsy,$enc,$R1,$R3,$BD2", []>; 2235 def InsnRX : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2236 bdxaddr12only:$XBD2), 2237 ".insn rx,$enc,$R1,$XBD2", []>; 2238 def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2239 bdxaddr12only:$XBD2), 2240 ".insn rxe,$enc,$R1,$XBD2", []>; 2241 def InsnRXF : DirectiveInsnRXF<(outs), 2242 (ins imm64zx48:$enc, AnyReg:$R1, 2243 AnyReg:$R3, bdxaddr12only:$XBD2), 2244 ".insn rxf,$enc,$R1,$R3,$XBD2", []>; 2245 def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2246 bdxaddr20only:$XBD2), 2247 ".insn rxy,$enc,$R1,$XBD2", []>; 2248 def InsnS : DirectiveInsnS<(outs), 2249 (ins imm64zx32:$enc, bdaddr12only:$BD2), 2250 ".insn s,$enc,$BD2", []>; 2251 def InsnSI : DirectiveInsnSI<(outs), 2252 (ins imm64zx32:$enc, bdaddr12only:$BD1, 2253 imm32sx8:$I2), 2254 ".insn si,$enc,$BD1,$I2", []>; 2255 def InsnSIY : DirectiveInsnSIY<(outs), 2256 (ins imm64zx48:$enc, 2257 bdaddr20only:$BD1, imm32zx8:$I2), 2258 ".insn siy,$enc,$BD1,$I2", []>; 2259 def InsnSIL : DirectiveInsnSIL<(outs), 2260 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2261 imm32zx16:$I2), 2262 ".insn sil,$enc,$BD1,$I2", []>; 2263 def InsnSS : DirectiveInsnSS<(outs), 2264 (ins imm64zx48:$enc, bdraddr12only:$RBD1, 2265 bdaddr12only:$BD2, AnyReg:$R3), 2266 ".insn ss,$enc,$RBD1,$BD2,$R3", []>; 2267 def InsnSSE : DirectiveInsnSSE<(outs), 2268 (ins imm64zx48:$enc, 2269 bdaddr12only:$BD1,bdaddr12only:$BD2), 2270 ".insn sse,$enc,$BD1,$BD2", []>; 2271 def InsnSSF : DirectiveInsnSSF<(outs), 2272 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2273 bdaddr12only:$BD2, AnyReg:$R3), 2274 ".insn ssf,$enc,$BD1,$BD2,$R3", []>; 2275 def InsnVRI : DirectiveInsnVRI<(outs), 2276 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, 2277 imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5), 2278 ".insn vri,$enc,$V1,$V2,$I3,$M4,$M5", []>; 2279 def InsnVRR : DirectiveInsnVRR<(outs), 2280 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, 2281 VR128:$V3, imm32zx4:$M4, imm32zx4:$M5, 2282 imm32zx4:$M6), 2283 ".insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>; 2284 def InsnVRS : DirectiveInsnVRS<(outs), 2285 (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V3, 2286 bdaddr12only:$BD2, imm32zx4:$M4), 2287 ".insn vrs,$enc,$BD2,$M4", []>; 2288 def InsnVRV : DirectiveInsnVRV<(outs), 2289 (ins imm64zx48:$enc, VR128:$V1, 2290 bdvaddr12only:$VBD2, imm32zx4:$M3), 2291 ".insn vrv,$enc,$V1,$VBD2,$M3", []>; 2292 def InsnVRX : DirectiveInsnVRX<(outs), 2293 (ins imm64zx48:$enc, VR128:$V1, 2294 bdxaddr12only:$XBD2, imm32zx4:$M3), 2295 ".insn vrx,$enc,$V1,$XBD2,$M3", []>; 2296 def InsnVSI : DirectiveInsnVSI<(outs), 2297 (ins imm64zx48:$enc, VR128:$V1, 2298 bdaddr12only:$BD2, imm32zx8:$I3), 2299 ".insn vsi,$enc,$V1,$BD2,$I3", []>; 2300} 2301 2302//===----------------------------------------------------------------------===// 2303// Peepholes. 2304//===----------------------------------------------------------------------===// 2305 2306// Avoid generating 2 XOR instructions. (xor (and x, y), y) is 2307// equivalent to (and (xor x, -1), y) 2308def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y), 2309 (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>; 2310 2311// Shift/rotate instructions only use the last 6 bits of the second operand 2312// register, so we can safely use NILL (16 fewer bits than NILF) to only AND the 2313// last 16 bits. 2314// Complexity is added so that we match this before we match NILF on the AND 2315// operation alone. 2316let AddedComplexity = 4 in { 2317 def : Pat<(shl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2318 (SLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2319 2320 def : Pat<(sra GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2321 (SRA GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2322 2323 def : Pat<(srl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2324 (SRL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2325 2326 def : Pat<(shl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2327 (SLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2328 2329 def : Pat<(sra GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2330 (SRAG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2331 2332 def : Pat<(srl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2333 (SRLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2334 2335 def : Pat<(rotl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2336 (RLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2337 2338 def : Pat<(rotl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2339 (RLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2340} 2341 2342// Substitute (x*64-s) with (-s), since shift/rotate instructions only 2343// use the last 6 bits of the second operand register (making it modulo 64). 2344let AddedComplexity = 4 in { 2345 def : Pat<(shl GR64:$val, (sub imm32mod64, GR32:$shift)), 2346 (SLLG GR64:$val, (LCR GR32:$shift), 0)>; 2347 2348 def : Pat<(sra GR64:$val, (sub imm32mod64, GR32:$shift)), 2349 (SRAG GR64:$val, (LCR GR32:$shift), 0)>; 2350 2351 def : Pat<(srl GR64:$val, (sub imm32mod64, GR32:$shift)), 2352 (SRLG GR64:$val, (LCR GR32:$shift), 0)>; 2353 2354 def : Pat<(rotl GR64:$val, (sub imm32mod64, GR32:$shift)), 2355 (RLLG GR64:$val, (LCR GR32:$shift), 0)>; 2356} 2357 2358// Peepholes for turning scalar operations into block operations. 2359defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence, 2360 XCSequence, 1>; 2361defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence, 2362 XCSequence, 2>; 2363defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence, 2364 XCSequence, 4>; 2365defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence, 2366 OCSequence, XCSequence, 1>; 2367defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence, 2368 XCSequence, 2>; 2369defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence, 2370 XCSequence, 4>; 2371defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence, 2372 XCSequence, 8>; 2373 2374//===----------------------------------------------------------------------===// 2375// Mnemonic Aliases 2376//===----------------------------------------------------------------------===// 2377 2378def JCT : MnemonicAlias<"jct", "brct">; 2379def JCTG : MnemonicAlias<"jctg", "brctg">; 2380def JAS : MnemonicAlias<"jas", "bras">; 2381def JASL : MnemonicAlias<"jasl", "brasl">; 2382def JXH : MnemonicAlias<"jxh", "brxh">; 2383def JXLE : MnemonicAlias<"jxle", "brxle">; 2384def JXHG : MnemonicAlias<"jxhg", "brxhg">; 2385def JXLEG : MnemonicAlias<"jxleg", "brxlg">; 2386 2387def BRU : MnemonicAlias<"bru", "j">; 2388def BRUL : MnemonicAlias<"brul", "jg", "att">; 2389def BRUL_HLASM : MnemonicAlias<"brul", "jlu", "hlasm">; 2390 2391foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 2392 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 2393 defm BRUAsm#V : MnemonicCondBranchAlias <CV<V>, "br#", "j#">; 2394 defm BRULAsm#V : MnemonicCondBranchAlias <CV<V>, "br#l", "jg#", "att">; 2395 defm BRUL_HLASMAsm#V : MnemonicCondBranchAlias <CV<V>, "br#l", "jl#", "hlasm">; 2396} 2397