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Searched refs:RD4 (Results 51 – 75 of 84) sorted by relevance

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/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_super.c149 RD4(sc, sc->base_reg, &reg); in super_mux_init()
177 RD4(sc, sc->base_reg, &reg); in super_mux_set_mux()
191 RD4(sc, sc->base_reg, &dummy); in super_mux_set_mux()
H A Dtegra210_clk_per.c669 RD4(sc, sc->base_reg, &reg); in periph_init()
710 RD4(sc, sc->base_reg, &reg); in periph_set_mux()
741 RD4(sc, sc->base_reg, &reg); in periph_recalc()
857 RD4(sc, get_enable_reg(sc->idx), &ena_reg); in pgate_init()
858 RD4(sc, get_reset_reg(sc->idx), &rst_reg); in pgate_init()
880 RD4(sc, base_reg, &reg); in pgate_set_gate()
898 RD4(sc, base_reg, &reg); in pgate_get_gate()
/freebsd/sys/arm/freescale/
H A Dfsl_ocotp.c99 RD4(struct ocotp_softc *sc, bus_size_t off) in RD4() function
172 return (RD4(ocotp_sc, off)); in fsl_ocotp_read_4()
/freebsd/sys/arm/allwinner/
H A Daw_sid.c232 #define RD4(sc, reg) bus_read_4((sc)->res, (reg)) macro
319 while (RD4(sc, SID_PRCTL) & SID_PRCTL_READ) in aw_sid_get_fuse()
321 val = RD4(sc, SID_RDKEY); in aw_sid_get_fuse()
323 val = RD4(sc, sc->sid_conf->efuses[i].base + in aw_sid_get_fuse()
H A Daw_usbphy.c162 #define RD4(res, o) bus_read_4(res, (o)) macro
164 #define CLR4(res, o, m) WR4(res, o, RD4(res, o) & ~(m))
165 #define SET4(res, o, m) WR4(res, o, RD4(res, o) | (m))
/freebsd/sys/arm/freescale/imx/
H A Dimx_epit.c133 RD4(struct epit_softc *sc, bus_size_t offset) in RD4() function
162 return (0xffffffff - RD4(sc, EPIT_CNR)); in epit_read_counter()
286 status = RD4(sc, EPIT_SR); in epit_intr()
459 while (RD4(sc, EPIT_CR) & EPIT_CR_SWR) in epit_attach()
/freebsd/sys/dev/clk/rockchip/
H A Drk_clk_mux.c48 #define RD4(_clk, off, val) \ macro
127 rv = RD4(clk, sc->offset, &reg); in rk_clk_mux_init()
158 RD4(clk, sc->offset, &reg); in rk_clk_mux_set_mux()
H A Drk_clk_fract.c40 #define RD4(_clk, off, val) \ macro
145 RD4(clk, sc->offset, &reg); in rk_clk_fract_init()
168 RD4(clk, sc->gate_offset, &val); in rk_clk_fract_set_gate()
/freebsd/sys/arm64/freescale/imx/clk/
H A Dimx_clk_gate.c41 #define RD4(_clk, off, val) \ macro
91 RD4(clk, sc->offset, &reg); in imx_clk_gate_set_gate()
/freebsd/sys/dev/mwl/
H A Dmwlhal.c508 RD4(mh, MACREG_REG_INT_CODE); in mwl_hal_intrset()
512 RD4(mh, MACREG_REG_INT_CODE); in mwl_hal_intrset()
529 dummy = RD4(mh, MACREG_REG_INT_CODE);
2173 v = RD4(mh, MACREG_REG_PROMISCUOUS); in mwl_hal_setpromisc()
2186 v = RD4(mh, MACREG_REG_PROMISCUOUS); in mwl_hal_getpromisc()
2284 *dp = RD4(mh, r); in mwl_hal_getregdump()
2292 *dp = RD4(mh, r); in mwl_hal_getregdump()
2351 RD4(mh, MACREG_REG_INT_CODE); in mwlSendCmd()
2450 RD4(mh, MACREG_REG_INT_CODE); in mwlTriggerPciCmd()
2453 RD4(mh, MACREG_REG_INT_CODE); in mwlTriggerPciCmd()
[all …]
/freebsd/sys/arm/nvidia/drm2/
H A Dtegra_dc.c563 val = RD4(sc, DC_WINC_WIN_OPTIONS); in dc_plane_disable()
752 val = RD4(sc, DC_CMD_DISPLAY_COMMAND); in dc_crtc_prepare()
777 val = RD4(sc, DC_CMD_INT_MASK); in dc_crtc_commit()
781 val = RD4(sc, DC_CMD_INT_ENABLE); in dc_crtc_commit()
846 val = RD4(sc, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
863 val = RD4(sc, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
894 base = RD4(sc, DC_WINBUF_START_ADDR); in dc_finish_page_flip()
1041 val = RD4(sc, DC_DISP_DISP_WIN_OPTIONS); in dc_cursor_set()
1045 val = RD4(sc, DC_DISP_DISP_WIN_OPTIONS); in dc_cursor_set()
1141 val = RD4(sc, DC_DISP_DISP_WIN_OPTIONS); in dc_hdmi_enable()
[all …]
/freebsd/sys/arm64/qoriq/
H A Dqoriq_therm.c204 RD4(struct qoriq_therm_softc *sc, bus_size_t addr) in RD4() function
221 val = RD4(sc, TMU_TRITSR(sensor->site_id)); in qoriq_therm_read_temp()
399 sc->ver = (RD4(sc, TMU_VERSION) >> 8) & 0xFF; in qoriq_therm_attach()
424 RD4(sc, TMU_TMR); in qoriq_therm_attach()
/freebsd/sys/riscv/riscv/
H A Dplic.c102 #define RD4(sc, reg) \ macro
172 pending = RD4(sc, PLIC_CLAIM(sc, cpu)); in plic_intr()
448 reg = RD4(sc, PLIC_ENABLE(sc, src->irq, cpu)); in plic_bind_intr()
465 reg = RD4(sc, PLIC_ENABLE(sc, src->irq, cpu)); in plic_bind_intr()
/freebsd/sys/arm/mv/
H A Dmv_ap806_clock.c100 #define RD4(sc, reg) SYSCON_READ_4((sc)->syscon, (reg)) macro
134 reg = RD4(sc, 0x400); in mv_ap806_clock_attach()
H A Dmv_cp110_clock.c134 #define RD4(sc, reg) SYSCON_READ_4((sc)->syscon, (reg)) macro
302 *val = RD4(sc, addr); in mv_cp110_clock_read_4()
314 reg = RD4(sc, addr); in mv_cp110_clock_modify_4()
H A Dmv_ap806_sei.c102 #define RD4(sc, reg) bus_read_4((sc)->mem_res, (reg)) macro
118 tmp = RD4(sc, GICP_SEMR(sisrc->irq)); in mv_ap806_sei_isrc_mask()
287 cause = RD4(sc, GICP_SECR1); in mv_ap806_sei_intr()
289 cause |= RD4(sc, GICP_SECR0); in mv_ap806_sei_intr()
H A Dmvebu_pinctrl.c106 #define RD4(sc, reg) SYSCON_READ_4((sc)->syscon, (reg)) macro
117 reg = RD4(sc, offset); in mv_pinctrl_configure_pin()
H A Dmv_cp110_icu.c99 #define RD4(sc, reg) bus_read_4((sc)->res, (reg)) macro
157 reg = RD4(sc, ICU_INT_CFG(i)); in mv_cp110_icu_attach()
191 reg = RD4(sc, ICU_INT_CFG(irq_no)); in mv_cp110_icu_convert_map_data()
/freebsd/sys/arm64/qoriq/clk/
H A Dqoriq_clk_pll.c52 #define RD4(_clk, offset, val) \ macro
78 RD4(clk, sc->offset, &mul); in qoriq_clk_pll_recalc_freq()
/freebsd/sys/dev/sdhci/
H A Dsdhci.c245 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); in sdhci_dumpregs_buf()
249 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2)); in sdhci_dumpregs_buf()
588 data = RD4(slot, SDHCI_BUFFER); in sdhci_read_block_pio()
603 data = RD4(slot, SDHCI_BUFFER); in sdhci_read_block_pio()
664 while (RD4(slot, SDHCI_PRESENT_STATE) & in sdhci_transfer_pio()
671 while (RD4(slot, SDHCI_PRESENT_STATE) & in sdhci_transfer_pio()
886 caps = RD4(slot, SDHCI_CAPABILITIES);
888 caps2 = RD4(slot, SDHCI_CAPABILITIES2);
1896 val = RD4(slot, SDHCI_RESPONSE + i * 4);
2167 val = RD4(slot, SDHCI_PRESENT_STATE);
[all …]
/freebsd/sys/dev/clk/
H A Dclk_div.c41 #define RD4(_clk, off, val) \ macro
124 rv = RD4(clk, sc->offset, &reg); in clknode_div_init()
229 RD4(clk, sc->offset, &reg); in clknode_div_set_freq()
/freebsd/sys/arm/broadcom/bcm2835/
H A Dbcm2835_sdhci.c432 RD4(struct bcm_sdhci_softc *sc, bus_size_t off) in RD4() function
456 uint32_t val = RD4(sc, off & ~3); in bcm_sdhci_read_1()
477 val32 = RD4(sc, off & ~3); in bcm_sdhci_read_2()
487 return RD4(sc, off); in bcm_sdhci_read_4()
504 uint32_t val32 = RD4(sc, off & ~3); in bcm_sdhci_write_1()
532 val32 = RD4(sc, off & ~3); in bcm_sdhci_write_2()
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_per.c556 RD4(sc, sc->base_reg, &reg); in periph_init()
596 RD4(sc, sc->base_reg, &reg); in periph_set_mux()
627 RD4(sc, sc->base_reg, &reg); in periph_recalc()
743 RD4(sc, get_enable_reg(sc->idx), &ena_reg); in pgate_init()
744 RD4(sc, get_reset_reg(sc->idx), &rst_reg); in pgate_init()
766 RD4(sc, base_reg, &reg); in pgate_set_gate()
784 RD4(sc, base_reg, &reg); in pgate_get_gate()
H A Dtegra124_car.h32 #define RD4(sc, reg, val) CLKDEV_READ_4((sc)->clkdev, reg, val) macro
/freebsd/sys/arm/nvidia/
H A Dtegra_sdhci.c119 RD4(struct tegra_sdhci_softc *sc, bus_size_t off) in RD4() function
213 RD4(sc, SDHCI_INT_STATUS); in tegra_sdhci_intr()
347 sc->caps = RD4(sc, SDHCI_CAPABILITIES); in tegra_sdhci_attach()

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