1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2018 Rubicon Communications, LLC (Netgate)
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/bus.h>
31
32 #include <sys/kernel.h>
33 #include <sys/module.h>
34 #include <sys/rman.h>
35 #include <sys/lock.h>
36 #include <sys/mutex.h>
37
38 #include <machine/bus.h>
39 #include <machine/resource.h>
40 #include <machine/intr.h>
41
42 #include <dev/clk/clk_fixed.h>
43 #include <dev/clk/clk_gate.h>
44 #include <dev/syscon/syscon.h>
45
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
48
49 #include <arm/mv/mv_cp110_clock.h>
50
51 #include "clkdev_if.h"
52 #include "syscon_if.h"
53
54 /* Clocks */
55 static struct clk_fixed_def cp110_clk_pll_0 = {
56 .clkdef.id = CP110_PLL_0,
57 .freq = 1000000000,
58 };
59
60 static const char *clk_parents_0[] = {"cp110-pll0-0"};
61 static const char *clk_parents_1[] = {"cp110-pll0-1"};
62
63 static struct clk_fixed_def cp110_clk_ppv2_core = {
64 .clkdef.id = CP110_PPV2_CORE,
65 .clkdef.parent_cnt = 1,
66 .mult = 1,
67 .div = 3,
68 };
69
70 static struct clk_fixed_def cp110_clk_x2core = {
71 .clkdef.id = CP110_X2CORE,
72 .clkdef.parent_cnt = 1,
73 .mult = 1,
74 .div = 2,
75 };
76
77 static const char *core_parents_0[] = {"cp110-x2core-0"};
78 static const char *core_parents_1[] = {"cp110-x2core-1"};
79
80 static struct clk_fixed_def cp110_clk_core = {
81 .clkdef.id = CP110_CORE,
82 .clkdef.parent_cnt = 1,
83 .mult = 1,
84 .div = 2,
85 };
86
87 static struct clk_fixed_def cp110_clk_sdio = {
88 .clkdef.id = CP110_SDIO,
89 .clkdef.parent_cnt = 1,
90 .mult = 2,
91 .div = 5,
92 };
93
94 /* Gates */
95
96 static struct cp110_gate cp110_gates[] = {
97 CCU_GATE(CP110_GATE_AUDIO, "cp110-gate-audio", 0)
98 CCU_GATE(CP110_GATE_COMM_UNIT, "cp110-gate-comm_unit", 1)
99 /* CCU_GATE(CP110_GATE_NAND, "cp110-gate-nand", 2) */
100 CCU_GATE(CP110_GATE_PPV2, "cp110-gate-ppv2", 3)
101 CCU_GATE(CP110_GATE_SDIO, "cp110-gate-sdio", 4)
102 CCU_GATE(CP110_GATE_MG, "cp110-gate-mg", 5)
103 CCU_GATE(CP110_GATE_MG_CORE, "cp110-gate-mg_core", 6)
104 CCU_GATE(CP110_GATE_XOR1, "cp110-gate-xor1", 7)
105 CCU_GATE(CP110_GATE_XOR0, "cp110-gate-xor0", 8)
106 CCU_GATE(CP110_GATE_GOP_DP, "cp110-gate-gop_dp", 9)
107 CCU_GATE(CP110_GATE_PCIE_X1_0, "cp110-gate-pcie_x10", 11)
108 CCU_GATE(CP110_GATE_PCIE_X1_1, "cp110-gate-pcie_x11", 12)
109 CCU_GATE(CP110_GATE_PCIE_X4, "cp110-gate-pcie_x4", 13)
110 CCU_GATE(CP110_GATE_PCIE_XOR, "cp110-gate-pcie_xor", 14)
111 CCU_GATE(CP110_GATE_SATA, "cp110-gate-sata", 15)
112 CCU_GATE(CP110_GATE_SATA_USB, "cp110-gate-sata_usb", 16)
113 CCU_GATE(CP110_GATE_MAIN, "cp110-gate-main", 17)
114 CCU_GATE(CP110_GATE_SDMMC_GOP, "cp110-gate-sdmmc_gop", 18)
115 CCU_GATE(CP110_GATE_SLOW_IO, "cp110-gate-slow_io", 21)
116 CCU_GATE(CP110_GATE_USB3H0, "cp110-gate-usb3h0", 22)
117 CCU_GATE(CP110_GATE_USB3H1, "cp110-gate-usb3h1", 23)
118 CCU_GATE(CP110_GATE_USB3DEV, "cp110-gate-usb3dev", 24)
119 CCU_GATE(CP110_GATE_EIP150, "cp110-gate-eip150", 25)
120 CCU_GATE(CP110_GATE_EIP197, "cp110-gate-eip197", 26)
121 };
122
123 struct mv_cp110_clock_softc {
124 device_t dev;
125 struct syscon *syscon;
126 struct mtx mtx;
127 };
128
129 static struct ofw_compat_data compat_data[] = {
130 {"marvell,cp110-clock", 1},
131 {NULL, 0}
132 };
133
134 #define RD4(sc, reg) SYSCON_READ_4((sc)->syscon, (reg))
135 #define WR4(sc, reg, val) SYSCON_WRITE_4((sc)->syscon, (reg), (val))
136
137 static char *
mv_cp110_clock_name(device_t dev,const char * name)138 mv_cp110_clock_name(device_t dev, const char *name)
139 {
140 char *clkname = NULL;
141 int unit;
142
143 unit = device_get_unit(dev);
144 if (asprintf(&clkname, M_DEVBUF, "%s-%d", name, unit) <= 0)
145 panic("Cannot generate unique clock name for %s\n", name);
146 return (clkname);
147 }
148
149 static int
mv_cp110_clock_probe(device_t dev)150 mv_cp110_clock_probe(device_t dev)
151 {
152
153 if (!ofw_bus_status_okay(dev))
154 return (ENXIO);
155
156 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
157 return (ENXIO);
158
159 device_set_desc(dev, "Marvell CP110 Clock Controller");
160 return (BUS_PROBE_DEFAULT);
161 }
162
163 static int
cp110_ofw_map(struct clkdom * clkdom,uint32_t ncells,phandle_t * cells,struct clknode ** clk)164 cp110_ofw_map(struct clkdom *clkdom, uint32_t ncells,
165 phandle_t *cells, struct clknode **clk)
166 {
167 int id = 0;
168
169 if (ncells != 2)
170 return (ENXIO);
171
172 id = cells[1];
173 if (cells[0] == 1)
174 id += CP110_MAX_CLOCK;
175
176 *clk = clknode_find_by_id(clkdom, id);
177
178 return (0);
179 }
180
181 static int
mv_cp110_clock_attach(device_t dev)182 mv_cp110_clock_attach(device_t dev)
183 {
184 struct mv_cp110_clock_softc *sc;
185 struct clkdom *clkdom;
186 struct clk_gate_def def;
187 char *pll0_name;
188 int unit, i;
189
190 sc = device_get_softc(dev);
191 sc->dev = dev;
192
193 if (SYSCON_GET_HANDLE(sc->dev, &sc->syscon) != 0 ||
194 sc->syscon == NULL) {
195 device_printf(dev, "cannot get syscon for device\n");
196 return (ENXIO);
197 }
198
199 unit = device_get_unit(dev);
200 if (unit > 1) {
201 device_printf(dev, "Bogus cp110-system-controller unit %d\n", unit);
202 return (ENXIO);
203 }
204
205 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
206
207 clkdom = clkdom_create(dev);
208 clkdom_set_ofw_mapper(clkdom, cp110_ofw_map);
209
210 pll0_name = mv_cp110_clock_name(dev, "cp110-pll0");
211 cp110_clk_pll_0.clkdef.name = pll0_name;
212 clknode_fixed_register(clkdom, &cp110_clk_pll_0);
213
214 cp110_clk_ppv2_core.clkdef.name = mv_cp110_clock_name(dev, "cp110-ppv2");
215 cp110_clk_ppv2_core.clkdef.parent_names = (unit == 0) ? clk_parents_0 : clk_parents_1;
216 clknode_fixed_register(clkdom, &cp110_clk_ppv2_core);
217
218 cp110_clk_x2core.clkdef.name = mv_cp110_clock_name(dev, "cp110-x2core");
219 cp110_clk_x2core.clkdef.parent_names = (unit == 0) ? clk_parents_0 : clk_parents_1;
220 clknode_fixed_register(clkdom, &cp110_clk_x2core);
221
222 cp110_clk_core.clkdef.name = mv_cp110_clock_name(dev, "cp110-core");
223 cp110_clk_core.clkdef.parent_names = (unit == 0) ? core_parents_0 : core_parents_1;
224 clknode_fixed_register(clkdom, &cp110_clk_core);
225
226 /* NAND missing */
227
228 cp110_clk_sdio.clkdef.name = mv_cp110_clock_name(dev, "cp110-sdio");
229 cp110_clk_sdio.clkdef.parent_names = (unit == 0) ? clk_parents_0 : clk_parents_1;
230 clknode_fixed_register(clkdom, &cp110_clk_sdio);
231
232 for (i = 0; i < nitems(cp110_gates); i++) {
233 if (cp110_gates[i].name == NULL)
234 continue;
235
236 memset(&def, 0, sizeof(def));
237 def.clkdef.id = CP110_MAX_CLOCK + i;
238 def.clkdef.name = mv_cp110_clock_name(dev, cp110_gates[i].name);
239 def.clkdef.parent_cnt = 1;
240 def.offset = CP110_CLOCK_GATING_OFFSET;
241 def.shift = cp110_gates[i].shift;
242 def.mask = 1;
243 def.on_value = 1;
244 def.off_value = 0;
245
246 switch (i) {
247 case CP110_GATE_MG:
248 case CP110_GATE_GOP_DP:
249 case CP110_GATE_PPV2:
250 def.clkdef.parent_names = &cp110_clk_ppv2_core.clkdef.name;
251 break;
252 case CP110_GATE_SDIO:
253 def.clkdef.parent_names = &cp110_clk_sdio.clkdef.name;
254 break;
255 case CP110_GATE_MAIN:
256 case CP110_GATE_PCIE_XOR:
257 case CP110_GATE_PCIE_X4:
258 case CP110_GATE_EIP150:
259 case CP110_GATE_EIP197:
260 def.clkdef.parent_names = &cp110_clk_x2core.clkdef.name;
261 break;
262 default:
263 def.clkdef.parent_names = &cp110_clk_core.clkdef.name;
264 break;
265 }
266
267 clknode_gate_register(clkdom, &def);
268 }
269
270 clkdom_finit(clkdom);
271
272 if (bootverbose)
273 clkdom_dump(clkdom);
274
275 return (0);
276 }
277
278 static int
mv_cp110_clock_detach(device_t dev)279 mv_cp110_clock_detach(device_t dev)
280 {
281
282 return (EBUSY);
283 }
284
285 static int
mv_cp110_clock_write_4(device_t dev,bus_addr_t addr,uint32_t val)286 mv_cp110_clock_write_4(device_t dev, bus_addr_t addr, uint32_t val)
287 {
288 struct mv_cp110_clock_softc *sc;
289
290 sc = device_get_softc(dev);
291 WR4(sc, addr, val);
292 return (0);
293 }
294
295 static int
mv_cp110_clock_read_4(device_t dev,bus_addr_t addr,uint32_t * val)296 mv_cp110_clock_read_4(device_t dev, bus_addr_t addr, uint32_t *val)
297 {
298 struct mv_cp110_clock_softc *sc;
299
300 sc = device_get_softc(dev);
301
302 *val = RD4(sc, addr);
303 return (0);
304 }
305
306 static int
mv_cp110_clock_modify_4(device_t dev,bus_addr_t addr,uint32_t clr,uint32_t set)307 mv_cp110_clock_modify_4(device_t dev, bus_addr_t addr, uint32_t clr, uint32_t set)
308 {
309 struct mv_cp110_clock_softc *sc;
310 uint32_t reg;
311
312 sc = device_get_softc(dev);
313
314 reg = RD4(sc, addr);
315 reg &= ~clr;
316 reg |= set;
317 WR4(sc, addr, reg);
318
319 return (0);
320 }
321
322 static void
mv_cp110_clock_device_lock(device_t dev)323 mv_cp110_clock_device_lock(device_t dev)
324 {
325 struct mv_cp110_clock_softc *sc;
326
327 sc = device_get_softc(dev);
328 mtx_lock(&sc->mtx);
329 }
330
331 static void
mv_cp110_clock_device_unlock(device_t dev)332 mv_cp110_clock_device_unlock(device_t dev)
333 {
334 struct mv_cp110_clock_softc *sc;
335
336 sc = device_get_softc(dev);
337 mtx_unlock(&sc->mtx);
338 }
339
340 static device_method_t mv_cp110_clock_methods[] = {
341 /* Device interface */
342 DEVMETHOD(device_probe, mv_cp110_clock_probe),
343 DEVMETHOD(device_attach, mv_cp110_clock_attach),
344 DEVMETHOD(device_detach, mv_cp110_clock_detach),
345
346 /* clkdev interface */
347 DEVMETHOD(clkdev_write_4, mv_cp110_clock_write_4),
348 DEVMETHOD(clkdev_read_4, mv_cp110_clock_read_4),
349 DEVMETHOD(clkdev_modify_4, mv_cp110_clock_modify_4),
350 DEVMETHOD(clkdev_device_lock, mv_cp110_clock_device_lock),
351 DEVMETHOD(clkdev_device_unlock, mv_cp110_clock_device_unlock),
352
353 DEVMETHOD_END
354 };
355
356 static driver_t mv_cp110_clock_driver = {
357 "mv_cp110_clock",
358 mv_cp110_clock_methods,
359 sizeof(struct mv_cp110_clock_softc),
360 };
361
362 EARLY_DRIVER_MODULE(mv_cp110_clock, simplebus, mv_cp110_clock_driver, 0, 0,
363 BUS_PASS_RESOURCE + BUS_PASS_ORDER_LATE);
364