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/dports/databases/mysql55-client/mysql-5.5.62/storage/ndb/include/kernel/
H A DInterpreter.hpp84 static Uint32 Add(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
85 static Uint32 Sub(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
175 Interpreter::Add(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Add() argument
176 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + ADD_REG_REG; in Add()
181 Interpreter::Sub(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Sub() argument
182 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + SUB_REG_REG; in Sub()
/dports/databases/mysql56-client/mysql-5.6.51/storage/ndb/include/kernel/
H A DInterpreter.hpp93 static Uint32 Add(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
94 static Uint32 Sub(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
216 Interpreter::Add(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Add() argument
217 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + ADD_REG_REG; in Add()
222 Interpreter::Sub(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Sub() argument
223 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + SUB_REG_REG; in Sub()
/dports/databases/mysqlwsrep56-server/mysql-wsrep-wsrep_5.6.51-25.33/storage/ndb/include/kernel/
H A DInterpreter.hpp93 static Uint32 Add(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
94 static Uint32 Sub(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
216 Interpreter::Add(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Add() argument
217 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + ADD_REG_REG; in Add()
222 Interpreter::Sub(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Sub() argument
223 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + SUB_REG_REG; in Sub()
/dports/databases/mysqlwsrep57-server/mysql-wsrep-wsrep_5.7.35-25.27/storage/ndb/include/kernel/
H A DInterpreter.hpp96 static Uint32 Add(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
97 static Uint32 Sub(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
220 Interpreter::Add(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Add() argument
221 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + ADD_REG_REG; in Add()
226 Interpreter::Sub(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Sub() argument
227 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + SUB_REG_REG; in Sub()
/dports/databases/percona-pam-for-mysql/percona-server-5.6.51-91.0/storage/ndb/include/kernel/
H A DInterpreter.hpp93 static Uint32 Add(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
94 static Uint32 Sub(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
216 Interpreter::Add(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Add() argument
217 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + ADD_REG_REG; in Add()
222 Interpreter::Sub(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Sub() argument
223 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + SUB_REG_REG; in Sub()
/dports/databases/percona56-client/percona-server-5.6.51-91.0/storage/ndb/include/kernel/
H A DInterpreter.hpp93 static Uint32 Add(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
94 static Uint32 Sub(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
216 Interpreter::Add(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Add() argument
217 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + ADD_REG_REG; in Add()
222 Interpreter::Sub(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Sub() argument
223 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + SUB_REG_REG; in Sub()
/dports/databases/percona56-server/percona-server-5.6.51-91.0/storage/ndb/include/kernel/
H A DInterpreter.hpp93 static Uint32 Add(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
94 static Uint32 Sub(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
216 Interpreter::Add(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Add() argument
217 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + ADD_REG_REG; in Add()
222 Interpreter::Sub(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Sub() argument
223 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + SUB_REG_REG; in Sub()
/dports/databases/percona57-client/percona-server-5.7.36-39/storage/ndb/include/kernel/
H A DInterpreter.hpp96 static Uint32 Add(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
97 static Uint32 Sub(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
220 Interpreter::Add(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Add() argument
221 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + ADD_REG_REG; in Add()
226 Interpreter::Sub(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Sub() argument
227 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + SUB_REG_REG; in Sub()
/dports/databases/percona57-pam-for-mysql/percona-server-5.7.36-39/storage/ndb/include/kernel/
H A DInterpreter.hpp96 static Uint32 Add(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
97 static Uint32 Sub(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
220 Interpreter::Add(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Add() argument
221 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + ADD_REG_REG; in Add()
226 Interpreter::Sub(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Sub() argument
227 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + SUB_REG_REG; in Sub()
/dports/databases/percona57-server/percona-server-5.7.36-39/storage/ndb/include/kernel/
H A DInterpreter.hpp96 static Uint32 Add(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
97 static Uint32 Sub(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
220 Interpreter::Add(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Add() argument
221 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + ADD_REG_REG; in Add()
226 Interpreter::Sub(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Sub() argument
227 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + SUB_REG_REG; in Sub()
/dports/databases/xtrabackup/percona-xtrabackup-2.4.21/storage/ndb/include/kernel/
H A DInterpreter.hpp96 static Uint32 Add(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
97 static Uint32 Sub(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
220 Interpreter::Add(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Add() argument
221 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + ADD_REG_REG; in Add()
226 Interpreter::Sub(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Sub() argument
227 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + SUB_REG_REG; in Sub()
/dports/databases/xtrabackup8/percona-xtrabackup-8.0.14/storage/ndb/include/kernel/
H A DInterpreter.hpp97 static Uint32 Add(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
98 static Uint32 Sub(Uint32 DstReg, Uint32 SrcReg1, Uint32 SrcReg2);
257 Interpreter::Add(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Add() argument
258 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + ADD_REG_REG; in Add()
263 Interpreter::Sub(Uint32 Dcoleg, Uint32 SrcReg1, Uint32 SrcReg2){ in Sub() argument
264 return (SrcReg1 << 6) + (SrcReg2 << 9) + (Dcoleg << 16) + SUB_REG_REG; in Sub()
/dports/devel/arm-elf-binutils/binutils-2.37/cpu/
H A Dmt.cpu588 (dni add "ADD DstReg, SrcReg1, SrcReg2"
623 (dni sub "SUB DstReg, SrcReg1, SrcReg2"
659 (dni mul "MUL DstReg, SrcReg1, SrcReg2"
700 (dni and "AND DstReg, SrcReg1, SrcReg2"
716 (dni or "OR DstReg, SrcReg1, SrcReg2"
740 (dni xor "XOR DstReg, SrcReg1, SrcReg2"
772 (dni nor "NOR DstReg, SrcReg1, SrcReg2"
814 (dni lsl "LSL DstReg, SrcReg1, SrcReg2"
830 (dni lsr "LSR DstReg, SrcReg1, SrcReg2"
846 (dni asr "ASR DstReg, SrcReg1, SrcReg2"
[all …]
/dports/devel/avr-gdb/gdb-7.3.1/cgen/cpu/
H A Dmt.cpu588 (dni add "ADD DstReg, SrcReg1, SrcReg2"
623 (dni sub "SUB DstReg, SrcReg1, SrcReg2"
659 (dni mul "MUL DstReg, SrcReg1, SrcReg2"
700 (dni and "AND DstReg, SrcReg1, SrcReg2"
716 (dni or "OR DstReg, SrcReg1, SrcReg2"
740 (dni xor "XOR DstReg, SrcReg1, SrcReg2"
772 (dni nor "NOR DstReg, SrcReg1, SrcReg2"
814 (dni lsl "LSL DstReg, SrcReg1, SrcReg2"
830 (dni lsr "LSR DstReg, SrcReg1, SrcReg2"
846 (dni asr "ASR DstReg, SrcReg1, SrcReg2"
[all …]
/dports/devel/avr-gdb/gdb-7.3.1/cpu/
H A Dmt.cpu588 (dni add "ADD DstReg, SrcReg1, SrcReg2"
623 (dni sub "SUB DstReg, SrcReg1, SrcReg2"
659 (dni mul "MUL DstReg, SrcReg1, SrcReg2"
700 (dni and "AND DstReg, SrcReg1, SrcReg2"
716 (dni or "OR DstReg, SrcReg1, SrcReg2"
740 (dni xor "XOR DstReg, SrcReg1, SrcReg2"
772 (dni nor "NOR DstReg, SrcReg1, SrcReg2"
814 (dni lsl "LSL DstReg, SrcReg1, SrcReg2"
830 (dni lsr "LSR DstReg, SrcReg1, SrcReg2"
846 (dni asr "ASR DstReg, SrcReg1, SrcReg2"
[all …]
/dports/devel/binutils/binutils-2.37/cpu/
H A Dmt.cpu588 (dni add "ADD DstReg, SrcReg1, SrcReg2"
623 (dni sub "SUB DstReg, SrcReg1, SrcReg2"
659 (dni mul "MUL DstReg, SrcReg1, SrcReg2"
700 (dni and "AND DstReg, SrcReg1, SrcReg2"
716 (dni or "OR DstReg, SrcReg1, SrcReg2"
740 (dni xor "XOR DstReg, SrcReg1, SrcReg2"
772 (dni nor "NOR DstReg, SrcReg1, SrcReg2"
814 (dni lsl "LSL DstReg, SrcReg1, SrcReg2"
830 (dni lsr "LSR DstReg, SrcReg1, SrcReg2"
846 (dni asr "ASR DstReg, SrcReg1, SrcReg2"
[all …]
/dports/devel/djgpp-binutils/binutils-2.17/cpu/
H A Dmt.cpu587 (dni add "ADD DstReg, SrcReg1, SrcReg2"
622 (dni sub "SUB DstReg, SrcReg1, SrcReg2"
658 (dni mul "MUL DstReg, SrcReg1, SrcReg2"
699 (dni and "AND DstReg, SrcReg1, SrcReg2"
715 (dni or "OR DstReg, SrcReg1, SrcReg2"
739 (dni xor "XOR DstReg, SrcReg1, SrcReg2"
771 (dni nor "NOR DstReg, SrcReg1, SrcReg2"
813 (dni lsl "LSL DstReg, SrcReg1, SrcReg2"
829 (dni lsr "LSR DstReg, SrcReg1, SrcReg2"
845 (dni asr "ASR DstReg, SrcReg1, SrcReg2"
[all …]
/dports/devel/gdb/gdb-11.1/cpu/
H A Dmt.cpu588 (dni add "ADD DstReg, SrcReg1, SrcReg2"
623 (dni sub "SUB DstReg, SrcReg1, SrcReg2"
659 (dni mul "MUL DstReg, SrcReg1, SrcReg2"
700 (dni and "AND DstReg, SrcReg1, SrcReg2"
716 (dni or "OR DstReg, SrcReg1, SrcReg2"
740 (dni xor "XOR DstReg, SrcReg1, SrcReg2"
772 (dni nor "NOR DstReg, SrcReg1, SrcReg2"
814 (dni lsl "LSL DstReg, SrcReg1, SrcReg2"
830 (dni lsr "LSR DstReg, SrcReg1, SrcReg2"
846 (dni asr "ASR DstReg, SrcReg1, SrcReg2"
[all …]
/dports/devel/gdb761/gdb-7.6.1/cpu/
H A Dmt.cpu588 (dni add "ADD DstReg, SrcReg1, SrcReg2"
623 (dni sub "SUB DstReg, SrcReg1, SrcReg2"
659 (dni mul "MUL DstReg, SrcReg1, SrcReg2"
700 (dni and "AND DstReg, SrcReg1, SrcReg2"
716 (dni or "OR DstReg, SrcReg1, SrcReg2"
740 (dni xor "XOR DstReg, SrcReg1, SrcReg2"
772 (dni nor "NOR DstReg, SrcReg1, SrcReg2"
814 (dni lsl "LSL DstReg, SrcReg1, SrcReg2"
830 (dni lsr "LSR DstReg, SrcReg1, SrcReg2"
846 (dni asr "ASR DstReg, SrcReg1, SrcReg2"
[all …]
/dports/devel/gnulibiberty/binutils-2.37/cpu/
H A Dmt.cpu588 (dni add "ADD DstReg, SrcReg1, SrcReg2"
623 (dni sub "SUB DstReg, SrcReg1, SrcReg2"
659 (dni mul "MUL DstReg, SrcReg1, SrcReg2"
700 (dni and "AND DstReg, SrcReg1, SrcReg2"
716 (dni or "OR DstReg, SrcReg1, SrcReg2"
740 (dni xor "XOR DstReg, SrcReg1, SrcReg2"
772 (dni nor "NOR DstReg, SrcReg1, SrcReg2"
814 (dni lsl "LSL DstReg, SrcReg1, SrcReg2"
830 (dni lsr "LSR DstReg, SrcReg1, SrcReg2"
846 (dni asr "ASR DstReg, SrcReg1, SrcReg2"
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1448 Register &SrcReg2, int &Mask, int &Value) const { in analyzeCompare() argument
1456 Register SrcReg2, int Mask, int Value, in optimizeCompareInstr() argument
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/CodeGen/
H A DPeepholeOptimizer.cpp610 Register SrcReg, SrcReg2; in optimizeCmpInstr() local
612 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) || in optimizeCmpInstr()
613 SrcReg.isPhysical() || SrcReg2.isPhysical()) in optimizeCmpInstr()
618 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) { in optimizeCmpInstr()
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp1054 SrcReg2 = MI.getOperand(2).getReg(); in analyzeCompare()
1063 SrcReg2 = 0; in analyzeCompare()
1073 SrcReg2 = 0; in analyzeCompare()
1253 if (CmpValue != 0 || SrcReg2 != 0) in optimizeCompareInstr()
4387 unsigned SrcReg2; in genFusedMultiply() local
4391 SrcReg2 = *ReplacedAddend; in genFusedMultiply()
4394 SrcReg2 = Root.getOperand(IdxOtherOpd).getReg(); in genFusedMultiply()
4404 if (Register::isVirtualRegister(SrcReg2)) in genFusedMultiply()
4405 MRI.constrainRegClass(SrcReg2, RC); in genFusedMultiply()
4415 .addReg(SrcReg2, getKillRegState(Src2IsKill)) in genFusedMultiply()
[all …]
H A DAArch64InstrInfo.h216 Register &SrcReg2, int &CmpMask,
221 Register SrcReg2, int CmpMask, int CmpValue,
H A DAArch64SIMDInstrOpt.cpp439 Register SrcReg2 = MI.getOperand(3).getReg(); in optimizeVectElement() local
445 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg2, LaneNumber, &DupDest)) { in optimizeVectElement()
448 .addReg(SrcReg2, Src2IsKill) in optimizeVectElement()

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