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Searched refs:csr (Results 1 – 25 of 106) sorted by relevance

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/freebsd/sys/powerpc/booke/
H A Dmachdep_e500.c56 uint32_t csr; in booke_enable_l1_cache() local
59 csr = mfspr(SPR_L1CSR0); in booke_enable_l1_cache()
60 if ((csr & L1CSR0_DCE) == 0) { in booke_enable_l1_cache()
65 csr = mfspr(SPR_L1CSR0); in booke_enable_l1_cache()
71 csr = mfspr(SPR_L1CSR1); in booke_enable_l1_cache()
77 csr = mfspr(SPR_L1CSR1); in booke_enable_l1_cache()
86 uint32_t csr; in booke_enable_l2_cache() local
91 csr = mfspr(SPR_L2CSR0); in booke_enable_l2_cache()
107 csr = mfspr(SPR_L2CSR0); in booke_enable_l2_cache()
117 uint32_t csr; in booke_enable_bpred() local
[all …]
H A Dmp_cpudep.c53 uint32_t msr, csr; in cpudep_ap_bootstrap() local
57 csr = mfspr(SPR_L1CSR0); in cpudep_ap_bootstrap()
58 if ((csr & L1CSR0_DCE) == 0) { in cpudep_ap_bootstrap()
63 csr = mfspr(SPR_L1CSR1); in cpudep_ap_bootstrap()
64 if ((csr & L1CSR1_ICE) == 0) { in cpudep_ap_bootstrap()
/freebsd/sys/dev/qat/qat_api/firmware/include/
H A Dicp_qat_hw_20_comp.h64 csr.algo, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
69 csr.sd, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
75 csr.edmm, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
80 csr.hbs, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
106 csr.abd, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
111 csr.lllbd, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
186 csr.lbms, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER()
196 csr.lazy, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER()
242 csr.hbs, in ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER()
263 csr.lbc, in ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER()
[all …]
/freebsd/sys/dev/qat/include/common/
H A Dicp_qat_hal.h144 #define CAP_CSR_ADDR(csr) (csr + handle->hal_cap_g_ctl_csr_addr_v) argument
146 ADF_CSR_WR(handle->hal_misc_addr_v, CAP_CSR_ADDR(csr), val)
148 ADF_CSR_RD(handle->hal_misc_addr_v, CAP_CSR_ADDR(csr))
153 SET_CAP_CSR((handle), (csr), (val)) : \
154 SET_CAP_CSR((handle), (csr) + GLOBAL_CSR, val); \
160 GET_CAP_CSR((handle), (csr)) : \
161 GET_CAP_CSR((handle), (csr) + GLOBAL_CSR); \
166 typeof(csr) csr_ = (csr); \
182 typeof(csr) csr_ = (csr); \
192 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & (csr))) argument
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/freebsd/sys/riscv/include/
H A Driscvreg.h191 #define csr_swap(csr, val) \ argument
196 __asm __volatile("csrrw %0, " #csr ", %1" \
201 #define csr_write(csr, val) \ argument
208 #define csr_set(csr, val) \ argument
215 #define csr_clear(csr, val) \ argument
222 #define csr_read(csr) \ argument
229 #define csr_read64(csr) \ argument
233 "csrr t0, " #csr "h\n" \
234 "csrr %0, " #csr "\n" \
235 "csrr %1, " #csr "h\n" \
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/freebsd/sys/dev/qat/qat_hw/qat_200xx/
H A Dadf_200xx_hw_data.c204 ADF_CSR_WR(csr, in adf_disable_error_interrupts()
208 ADF_CSR_WR(csr, in adf_disable_error_interrupts()
243 adf_csr_fetch_and_and(csr, in adf_enable_mmp_error_correction()
254 adf_csr_fetch_and_or(csr, in adf_enable_mmp_error_correction()
261 adf_csr_fetch_and_or(csr, in adf_enable_mmp_error_correction()
271 adf_csr_fetch_and_and(csr, in adf_enable_mmp_error_correction()
278 adf_csr_fetch_and_and(csr, in adf_enable_mmp_error_correction()
285 adf_csr_fetch_and_or(csr, in adf_enable_mmp_error_correction()
290 ADF_CSR_WR(csr, in adf_enable_mmp_error_correction()
331 ADF_CSR_WR(csr, ADF_PPERR(i), val); in adf_enable_error_correction()
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/freebsd/sys/dev/usb/controller/
H A Dmusb_otg.c403 uint8_t csr; in musbotg_dev_ctrl_setup_rx() local
529 uint8_t csr, csrh; in musbotg_host_ctrl_setup_tx() local
638 uint8_t csr; in musbotg_dev_ctrl_data_rx() local
779 uint8_t csr; in musbotg_dev_ctrl_data_tx() local
895 uint8_t csr; in musbotg_host_ctrl_data_rx() local
1073 uint8_t csr, csrh; in musbotg_host_ctrl_data_tx() local
1243 uint8_t csr; in musbotg_dev_ctrl_status() local
1365 uint8_t csr; in musbotg_host_ctrl_status_tx() local
1433 uint8_t csr; in musbotg_dev_data_rx() local
1581 uint8_t csr; in musbotg_dev_data_tx() local
[all …]
/freebsd/sys/dev/qat/qat_common/
H A Dadf_hw_arbiter.c88 WRITE_CSR_ARB_WRK_2_SER_MAP(csr, in adf_init_gen2_arb()
162 struct resource *csr = csr_addr; in adf_disable_ring_arb() local
169 arbenable = csr_ops->read_csr_ring_srv_arb_en(csr, bank_nr); in adf_disable_ring_arb()
181 struct resource *csr; in adf_exit_arb() local
187 csr = accel_dev->transport->banks[0].csr_addr; in adf_exit_arb()
193 WRITE_CSR_ARB_SARCONFIG(csr, info.arbiter_offset, i, 0); in adf_exit_arb()
198 WRITE_CSR_ARB_WRK_2_SER_MAP(csr, in adf_exit_arb()
207 csr_ops->write_csr_ring_srv_arb_en(csr, i, 0); in adf_exit_arb()
214 struct resource *csr; in adf_disable_arb() local
220 csr = accel_dev->transport->banks[0].csr_addr; in adf_disable_arb()
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H A Dadf_dev_err.c178 struct resource *csr = misc_bar->virt_addr; in adf_print_err_registers() local
184 val = ADF_CSR_RD(csr, adf_err_regs[i].offs); in adf_print_err_registers()
196 val = adf_accel_err_regs[i].read(csr, accel); in adf_print_err_registers()
224 struct resource *csr, in adf_handle_slice_hang() argument
227 u32 slice_hang = ADF_CSR_RD(csr, slice_hang_offset); in adf_handle_slice_hang()
264 ADF_CSR_WR(csr, slice_hang_offset, slice_hang); in adf_handle_slice_hang()
280 struct resource *csr = misc_bar->virt_addr; in adf_check_slice_hang() local
281 u32 errsou3 = ADF_CSR_RD(csr, ADF_ERRSOU3); in adf_check_slice_hang()
282 u32 errsou5 = ADF_CSR_RD(csr, ADF_ERRSOU5); in adf_check_slice_hang()
306 if (ADF_CSR_RD(csr, ADF_INTSTATSSM(accel_num)) & in adf_check_slice_hang()
[all …]
H A Dadf_freebsd_transport_debug.c23 struct resource *csr = ring->bank->csr_addr; in adf_ring_show() local
32 head = csr_ops->read_csr_ring_head(csr, in adf_ring_show()
35 tail = csr_ops->read_csr_ring_tail(csr, in adf_ring_show()
38 empty = csr_ops->read_csr_e_stat(csr, bank->bank_number); in adf_ring_show()
139 struct resource *csr = bank->csr_addr; in adf_bank_show() local
145 head = csr_ops->read_csr_ring_head(csr, in adf_bank_show()
148 tail = csr_ops->read_csr_ring_tail(csr, in adf_bank_show()
151 empty = csr_ops->read_csr_e_stat(csr, bank->bank_number); in adf_bank_show()
H A Dqat_hal.c112 unsigned int csr, in qat_hal_rd_ae_csr() argument
130 unsigned int csr, in qat_hal_wr_ae_csr() argument
208 unsigned int csr, new_csr; in qat_hal_set_ae_ctx_mode() local
217 csr = IGNORE_W1C_MASK & csr; in qat_hal_set_ae_ctx_mode()
237 csr &= IGNORE_W1C_MASK; in qat_hal_set_ae_nn_mode()
242 if (new_csr != csr) in qat_hal_set_ae_nn_mode()
257 csr &= IGNORE_W1C_MASK; in qat_hal_set_ae_lm_mode()
280 if (new_csr != csr) in qat_hal_set_ae_lm_mode()
293 csr &= IGNORE_W1C_MASK; in qat_hal_set_ae_tindex_mode()
296 if (new_csr != csr) in qat_hal_set_ae_tindex_mode()
[all …]
H A Dadf_gen4_hw_data.c154 reset_ring_pair(struct resource *csr, u32 bank_number) in reset_ring_pair() argument
166 ADF_CSR_WR(csr, in reset_ring_pair()
172 val = ADF_CSR_RD(csr, ADF_WQM_CSR_RPRESETSTS(bank_number)); in reset_ring_pair()
182 ADF_CSR_WR(csr, in reset_ring_pair()
193 struct resource *csr; in adf_gen4_ring_pair_reset() local
199 csr = (&GET_BARS(accel_dev)[etr_bar_id])->virt_addr; in adf_gen4_ring_pair_reset()
201 ret = reset_ring_pair(csr, bank_number); in adf_gen4_ring_pair_reset()
/freebsd/crypto/openssl/test/certs/
H A Dmkcert.sh113 csr=$(req "$key" "CN = $cn") || return 1
114 echo "$csr" |
155 echo "$csr" |
176 echo "$csr" |
265 echo "$csr" |
299 echo "$csr" |
345 echo "$csr" |
354 csr=$(req_nocn "$key") || return 1
355 echo "$csr" |
388 echo "$csr" |
[all …]
/freebsd/sys/dev/qat/qat_hw/qat_c4xxx/
H A Dadf_c4xxx_res_part.c64 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_enable_sym_threads() local
73 WRITE_CSR_WQM(csr, in adf_enable_sym_threads()
82 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_enable_asym_threads() local
93 WRITE_CSR_WQM(csr, in adf_enable_asym_threads()
102 struct resource *csr = accel_dev->transport->banks[0].csr_addr; in adf_enable_dc_threads() local
111 WRITE_CSR_WQM(csr, in adf_enable_dc_threads()
136 WRITE_CSR_WQM(csr, in adf_init_arb_c4xxx()
170 struct resource *csr; in adf_exit_arb_c4xxx() local
176 csr = accel_dev->transport->banks[0].csr_addr; in adf_exit_arb_c4xxx()
180 WRITE_CSR_WQM(csr, in adf_exit_arb_c4xxx()
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H A Dadf_c4xxx_hw_data.c230 ADF_CSR_WR(csr, in c4xxx_set_ssm_wdtimer()
289 csr, in c4xxx_check_slice_hang()
299 csr, in c4xxx_check_slice_hang()
503 ADF_CSR_WR(csr, in adf_enable_error_interrupts()
511 ADF_CSR_WR(csr, in adf_enable_error_interrupts()
516 ADF_CSR_WR(csr, in adf_enable_error_interrupts()
521 ADF_CSR_WR(csr, in adf_enable_error_interrupts()
526 ADF_CSR_WR(csr, in adf_enable_error_interrupts()
529 ADF_CSR_WR(csr, in adf_enable_error_interrupts()
593 csr, in adf_enable_mmp_error_correction()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/apm/
H A Dapm-storm.dtsi197 csr-mask = <0x2>;
234 csr-mask = <0xa>;
245 csr-mask = <0x3>;
256 csr-mask = <0x3>;
269 csr-mask = <0x00>;
283 csr-mask = <0x3a>;
297 csr-mask = <0x3a>;
310 csr-mask = <0x05>;
323 csr-mask = <0x05>;
336 csr-mask = <0x05>;
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/freebsd/crypto/openssl/test/testutil/
H A Dload.c94 X509_REQ *csr = NULL; in load_csr_der() local
100 csr = X509_REQ_new_ex(libctx, NULL); in load_csr_der()
101 if (TEST_ptr(csr)) in load_csr_der()
102 (void)TEST_ptr(d2i_X509_REQ_bio(bio, &csr)); in load_csr_der()
104 return csr; in load_csr_der()
/freebsd/sys/dev/iicbus/rtc/
H A Dnxprtc.c441 struct csr { in pcf8523_start() struct
446 } csr; in pcf8523_start() local
451 if ((err = nxprtc_readfrom(sc->dev, PCF85xx_R_CS1, &csr, in pcf8523_start()
452 sizeof(csr), WAITFLAGS)) != 0){ in pcf8523_start()
464 (csr.cs1 & PCF85xx_B_CS1_STOP) || (csr.sec & PCF85xx_B_SECOND_OS)) { in pcf8523_start()
529 if (csr.cs1 & PCF2129_B_CS1_12HR) in pcf8523_start()
547 if (csr.cs1 & PCF8523_B_CS1_12HR) in pcf8523_start()
615 struct csr { in pcf8563_start() struct
619 } csr; in pcf8563_start() local
624 sizeof(csr), WAITFLAGS)) != 0){ in pcf8563_start()
[all …]
/freebsd/sys/dev/qat/qat_hw/qat_dh895xcc/
H A Dadf_dh895xcc_hw_data.c198 struct resource *csr = misc_bar->virt_addr; in adf_enable_error_correction() local
207 val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_CTX_ENABLES(i)); in adf_enable_error_correction()
209 ADF_CSR_WR(csr, ADF_DH895XCC_AE_CTX_ENABLES(i), val); in adf_enable_error_correction()
210 val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_MISC_CONTROL(i)); in adf_enable_error_correction()
212 ADF_CSR_WR(csr, ADF_DH895XCC_AE_MISC_CONTROL(i), val); in adf_enable_error_correction()
220 val = ADF_CSR_RD(csr, ADF_DH895XCC_UERRSSMSH(i)); in adf_enable_error_correction()
222 ADF_CSR_WR(csr, ADF_DH895XCC_UERRSSMSH(i), val); in adf_enable_error_correction()
223 val = ADF_CSR_RD(csr, ADF_DH895XCC_CERRSSMSH(i)); in adf_enable_error_correction()
225 ADF_CSR_WR(csr, ADF_DH895XCC_CERRSSMSH(i), val); in adf_enable_error_correction()
/freebsd/sys/dev/qat/qat_hw/qat_c62x/
H A Dadf_c62x_hw_data.c185 struct resource *csr = misc_bar->virt_addr; in adf_enable_error_correction() local
194 val = ADF_CSR_RD(csr, ADF_C62X_AE_CTX_ENABLES(i)); in adf_enable_error_correction()
196 ADF_CSR_WR(csr, ADF_C62X_AE_CTX_ENABLES(i), val); in adf_enable_error_correction()
197 val = ADF_CSR_RD(csr, ADF_C62X_AE_MISC_CONTROL(i)); in adf_enable_error_correction()
199 ADF_CSR_WR(csr, ADF_C62X_AE_MISC_CONTROL(i), val); in adf_enable_error_correction()
207 val = ADF_CSR_RD(csr, ADF_C62X_UERRSSMSH(i)); in adf_enable_error_correction()
209 ADF_CSR_WR(csr, ADF_C62X_UERRSSMSH(i), val); in adf_enable_error_correction()
210 val = ADF_CSR_RD(csr, ADF_C62X_CERRSSMSH(i)); in adf_enable_error_correction()
212 ADF_CSR_WR(csr, ADF_C62X_CERRSSMSH(i), val); in adf_enable_error_correction()
/freebsd/sys/dev/qat/qat_hw/qat_c3xxx/
H A Dadf_c3xxx_hw_data.c181 struct resource *csr = misc_bar->virt_addr; in adf_enable_error_correction() local
190 val = ADF_CSR_RD(csr, ADF_C3XXX_AE_CTX_ENABLES(i)); in adf_enable_error_correction()
192 ADF_CSR_WR(csr, ADF_C3XXX_AE_CTX_ENABLES(i), val); in adf_enable_error_correction()
193 val = ADF_CSR_RD(csr, ADF_C3XXX_AE_MISC_CONTROL(i)); in adf_enable_error_correction()
195 ADF_CSR_WR(csr, ADF_C3XXX_AE_MISC_CONTROL(i), val); in adf_enable_error_correction()
203 val = ADF_CSR_RD(csr, ADF_C3XXX_UERRSSMSH(i)); in adf_enable_error_correction()
205 ADF_CSR_WR(csr, ADF_C3XXX_UERRSSMSH(i), val); in adf_enable_error_correction()
206 val = ADF_CSR_RD(csr, ADF_C3XXX_CERRSSMSH(i)); in adf_enable_error_correction()
208 ADF_CSR_WR(csr, ADF_C3XXX_CERRSSMSH(i), val); in adf_enable_error_correction()
/freebsd/sys/powerpc/mpc85xx/
H A Dmpc85xx.c294 uint32_t csr, size, ver; in mpc85xx_enable_l3_cache() local
300 csr = ccsr_read4(OCP85XX_CPC_CSR0); in mpc85xx_enable_l3_cache()
301 if ((csr & OCP85XX_CPC_CSR0_CE) == 0) { in mpc85xx_enable_l3_cache()
306 csr = ccsr_read4(OCP85XX_CPC_CSR0); in mpc85xx_enable_l3_cache()
308 (csr & OCP85XX_CPC_CSR0_CE) == 0) { in mpc85xx_enable_l3_cache()
311 size, (csr & OCP85XX_CPC_CSR0_CE) == 0 ? in mpc85xx_enable_l3_cache()
/freebsd/sys/dev/mii/
H A Dlxtphy.c194 int bmcr, bmsr, csr; in lxtphy_status() local
204 csr = PHY_READ(sc, MII_LXTPHY_CSR); in lxtphy_status()
205 if (csr & CSR_LINK) in lxtphy_status()
225 if (csr & CSR_SPEED) in lxtphy_status()
229 if (csr & CSR_DUPLEX) in lxtphy_status()
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dfsl,imx8qxp-csr.yaml4 $id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml#
28 - fsl,imx8qxp-mipi-lvds-csr
29 - fsl,imx8qm-lvds-csr
58 const: fsl,imx8qxp-mipi-lvds-csr
68 const: fsl,imx8qm-lvds-csr
81 compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd";
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dxgene.txt40 may include "csr-reg" and/or "div-reg". If this property
42 only "csr-reg".
49 - csr-offset : Offset to the CSR reset register from the reset address base.
51 - csr-mask : CSR reset mask bit. Default is 0xF.
96 reg-name = "csr-reg";
120 reg-names = "csr-reg", "div-reg";
121 csr-offset = <0x0>;
122 csr-mask = <0x200>;

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