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Searched refs:csr (Results 1 – 25 of 26) sorted by relevance

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/qemu/hw/net/
H A Dpcnet.c604 s->csr[12] & 0xff, s->csr[12] >> 8, in padr_match()
605 s->csr[13] & 0xff, s->csr[13] >> 8, in padr_match()
606 s->csr[14] & 0xff, s->csr[14] >> 8 in padr_match()
635 (s->csr[8] | s->csr[9] | s->csr[10] | s->csr[11]) != 0) { in ladr_match()
637 s->csr[8] & 0xff, s->csr[8] >> 8, in ladr_match()
638 s->csr[9] & 0xff, s->csr[9] >> 8, in ladr_match()
640 s->csr[11] & 0xff, s->csr[11] >> 8 in ladr_match()
875 s->csr[28] = s->csr[29] = 0; in pcnet_rdte_poll()
948 s->csr[34] = s->csr[35] = 0; in pcnet_tdte_poll()
957 s->csr[60] = s->csr[34]; in pcnet_tdte_poll()
[all …]
H A Dtulip.c29 uint32_t csr[16]; member
108 uint32_t ie = s->csr[5] & s->csr[7]; in tulip_update_int()
123 assert = s->csr[5] & s->csr[7] & (CSR5_AIS | CSR5_NIS); in tulip_update_int()
124 trace_tulip_irq(s->csr[5], s->csr[7], assert ? "assert" : "deassert"); in tulip_update_int()
522 return s->csr[9]; in tulip_csr9_read()
757 s->csr[0] = data; in tulip_write()
795 s->csr[6] = data; in tulip_write()
812 s->csr[7] = data; in tulip_write()
817 s->csr[9] = data; in tulip_write()
830 s->csr[10] = data; in tulip_write()
[all …]
H A Dpcnet.h42 uint16_t csr[128]; member
/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_privileged.c.inc8 #include "cpu-csr.h"
165 const CSRInfo *csr;
174 return csr;
193 const CSRInfo *csr;
198 csr = get_csr(a->csr);
199 if (csr == NULL) {
218 const CSRInfo *csr;
223 csr = get_csr(a->csr);
224 if (csr == NULL) {
254 csr = get_csr(a->csr);
[all …]
/qemu/hw/usb/
H A Dhcd-musb.c292 uint16_t csr[2]; member
751 ep->csr[1] &= ~MGC_M_RXCSR_H_REQPKT; in musb_rx_packet_complete()
768 ep->csr[1] |= MGC_M_RXCSR_H_RXSTALL; in musb_rx_packet_complete()
784 ep->csr[1] |= MGC_M_RXCSR_DATAERROR; in musb_rx_packet_complete()
797 ep->csr[1] |= MGC_M_RXCSR_H_ERROR; in musb_rx_packet_complete()
950 ep->csr[1] &= ~MGC_M_RXCSR_FIFOFULL; in musb_read_fifo()
1128 return s->ep[ep].csr[0]; in musb_ep_readh()
1132 ret = s->ep[ep].csr[1]; in musb_ep_readh()
1173 s->ep[ep].csr[0] &= in musb_ep_writeh()
1176 s->ep[ep].csr[0] &= in musb_ep_writeh()
[all …]
/qemu/target/riscv/insn_trans/
H A Dtrans_rvi.c.inc842 TCGv_i32 csr = tcg_constant_i32(rc);
845 gen_helper_csrr(dest, tcg_env, csr);
852 TCGv_i32 csr = tcg_constant_i32(rc);
855 gen_helper_csrw(tcg_env, csr, src);
862 TCGv_i32 csr = tcg_constant_i32(rc);
874 TCGv_i32 csr = tcg_constant_i32(rc);
877 gen_helper_csrr_i128(destl, tcg_env, csr);
885 TCGv_i32 csr = tcg_constant_i32(rc);
897 TCGv_i32 csr = tcg_constant_i32(rc);
917 return do_csrw(ctx, a->csr, src);
[all …]
/qemu/hw/misc/
H A Dnpcm7xx_pwm.c74 uint32_t csr; in npcm7xx_pwm_calculate_freq() local
81 csr = NPCM7XX_CSR(p->module->csr, p->index); in npcm7xx_pwm_calculate_freq()
86 if (csr > 4) { in npcm7xx_pwm_calculate_freq()
89 __func__, csr); in npcm7xx_pwm_calculate_freq()
90 csr = 4; in npcm7xx_pwm_calculate_freq()
93 if (csr < 4) { in npcm7xx_pwm_calculate_freq()
94 freq >>= csr + 1; in npcm7xx_pwm_calculate_freq()
169 uint32_t old_csr = s->csr; in npcm7xx_pwm_write_csr()
172 s->csr = new_csr; in npcm7xx_pwm_write_csr()
324 value = s->csr; in npcm7xx_pwm_read()
[all …]
H A Dstm32l4x5_rcc.c397 val = extract32(s->csr, R_CSR_MSISRANGE_SHIFT, R_CSR_MSISRANGE_LENGTH); in rcc_update_msi()
890 val = FIELD_EX32(s->csr, CSR, LSION); in rcc_update_csr()
893 s->csr |= R_CSR_LSIRDY_MASK; in rcc_update_csr()
904 s->csr &= ~R_CSR_LSIRDY_MASK; in rcc_update_csr()
946 s->csr = 0x0C000600; in stm32l4x5_rcc_reset_hold()
1044 retvalue = s->csr; in stm32l4x5_rcc_read()
1204 s->csr = value & ~CSR_READ_ONLY_MASK; in stm32l4x5_rcc_write()
1361 VMSTATE_UINT32(csr, Stm32l4x5RccState),
/qemu/target/riscv/
H A Dop_helper.c42 target_ulong helper_csrr(CPURISCVState *env, int csr) in helper_csrr() argument
49 if (csr == CSR_SEED) { in helper_csrr()
54 RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0); in helper_csrr()
62 void helper_csrw(CPURISCVState *env, int csr, target_ulong src) in helper_csrw() argument
72 target_ulong helper_csrrw(CPURISCVState *env, int csr, in helper_csrrw() argument
84 target_ulong helper_csrr_i128(CPURISCVState *env, int csr) in helper_csrr_i128() argument
87 RISCVException ret = riscv_csrrw_i128(env, csr, &rv, in helper_csrr_i128()
99 void helper_csrw_i128(CPURISCVState *env, int csr, in helper_csrw_i128() argument
102 RISCVException ret = riscv_csrrw_i128(env, csr, NULL, in helper_csrw_i128()
111 target_ulong helper_csrrw_i128(CPURISCVState *env, int csr, in helper_csrrw_i128() argument
[all …]
H A Dinsn32.decode28 %csr 20:12
69 @csr ............ ..... ... ..... ....... %csr %rs1 %rd
163 csrrw ............ ..... 001 ..... 1110011 @csr
164 csrrs ............ ..... 010 ..... 1110011 @csr
165 csrrc ............ ..... 011 ..... 1110011 @csr
166 csrrwi ............ ..... 101 ..... 1110011 @csr
167 csrrsi ............ ..... 110 ..... 1110011 @csr
168 csrrci ............ ..... 111 ..... 1110011 @csr
H A Dmeson.build14 'csr.c',
/qemu/tests/qtest/
H A Dnpcm7xx_pwm-test.c319 static uint32_t pwm_selector(uint32_t csr) in pwm_selector() argument
321 switch (csr) { in pwm_selector()
575 uint32_t ppr, csr, pcr; in test_oneshot() local
584 csr = csr_list[j]; in test_oneshot()
585 pwm_write_csr(qts, td, csr); in test_oneshot()
589 g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr); in test_oneshot()
606 uint32_t ppr, csr, pcr, cnr, cmr; in test_toggle() local
619 csr = csr_list[j]; in test_toggle()
620 pwm_write_csr(qts, td, csr); in test_toggle()
629 expected_freq = pwm_compute_freq(qts, ppr, csr, cnr); in test_toggle()
[all …]
/qemu/hw/m68k/
H A Dnext-cube.c48 uint32_t csr; member
511 next_state->dma[NEXTDMA_ENRX].csr |= DMA_DEV2M; in next_dma_write()
516 next_state->dma[NEXTDMA_ENRX].csr |= DMA_ENABLE; in next_dma_write()
519 next_state->dma[NEXTDMA_ENRX].csr |= DMA_SUPDATE; in next_dma_write()
522 next_state->dma[NEXTDMA_ENRX].csr &= ~DMA_COMPLETE; in next_dma_write()
546 next_state->dma[NEXTDMA_SCSI].csr |= DMA_DEV2M; in next_dma_write()
550 next_state->dma[NEXTDMA_SCSI].csr |= DMA_ENABLE; in next_dma_write()
553 next_state->dma[NEXTDMA_SCSI].csr |= DMA_SUPDATE; in next_dma_write()
600 val = next_state->dma[NEXTDMA_SCSI].csr; in next_dma_read()
604 val = next_state->dma[NEXTDMA_ENRX].csr; in next_dma_read()
[all …]
/qemu/hw/timer/
H A Dxilinx_timer.c93 uint32_t csr; in timer_update_irq() local
96 csr = t->timers[i].regs[R_TCSR]; in timer_update_irq()
97 irq |= (csr & TCSR_TINT) && (csr & TCSR_ENIT); in timer_update_irq()
/qemu/linux-user/loongarch64/
H A Dtarget_syscall.h29 } csr; member
H A Dcpu_loop.c107 env->pc = regs->csr.era; in target_cpu_copy_regs()
/qemu/include/hw/misc/
H A Dnpcm7xx_pwm.h97 uint32_t csr; member
H A Dstm32l4x5_rcc.h215 uint32_t csr; member
/qemu/hw/i386/
H A Dintel_iommu.c84 stq_le_p(&s->csr[addr], val); in vtd_define_quad()
97 stl_le_p(&s->csr[addr], val); in vtd_define_long()
113 stq_le_p(&s->csr[addr], in vtd_set_quad()
122 stl_le_p(&s->csr[addr], in vtd_set_long()
128 uint64_t val = ldq_le_p(&s->csr[addr]); in vtd_get_quad()
143 return ldq_le_p(&s->csr[addr]); in vtd_get_quad_raw()
148 return ldl_le_p(&s->csr[addr]); in vtd_get_long_raw()
153 stq_le_p(&s->csr[addr], val); in vtd_set_quad_raw()
160 stl_le_p(&s->csr[addr], new_val); in vtd_set_clear_mask_long()
168 stq_le_p(&s->csr[addr], new_val); in vtd_set_clear_mask_quad()
[all …]
/qemu/include/hw/i386/
H A Dintel_iommu.h257 uint8_t csr[DMAR_REG_SIZE]; /* register values */ member
/qemu/target/riscv/kvm/
H A Dkvm-cpu.c133 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ argument
135 int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), &reg); \
141 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ argument
143 int _ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), &reg); \
/qemu/target/loongarch/
H A Dinsns.decode49 &r_csr rd csr
50 &rr_csr rd rj csr
98 @r_csr .... .... csr:14 ..... rd:5 &r_csr
99 @rr_csr .... .... csr:14 rj:5 rd:5 &rr_csr
H A Ddisas.c317 output(ctx, mnemonic, "r%d, %d # %s", a->rd, a->csr, get_csr_name(a->csr)); in output_r_csr()
324 a->rd, a->rj, a->csr, get_csr_name(a->csr)); in output_rr_csr()
/qemu/hw/vfio/
H A Dpci.c2119 uint16_t csr = pci_get_word(vdev->pdev.config + pos + PCI_PM_CTRL); in vfio_check_pm_reset() local
2121 if (!(csr & PCI_PM_CTRL_NO_SOFT_RESET)) { in vfio_check_pm_reset()
/qemu/linux-user/
H A Delfload.c1248 regs->csr.crmd = 2 << 3; in init_thread()
1249 regs->csr.era = infop->entry; in init_thread()

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