| /dragonfly/sys/dev/drm/i915/ |
| H A D | intel_cdclk.c | 521 u32 divider; in vlv_set_cdclk() local
529 val |= divider; in vlv_set_cdclk()
1186 u32 divider; in bxt_get_cdclk() local
1198 switch (divider) { in bxt_get_cdclk()
1213 MISSING_CASE(divider); in bxt_get_cdclk()
1261 u32 val, divider; in bxt_set_cdclk() local
1470 u32 divider; in cnl_get_cdclk() local
1482 switch (divider) { in cnl_get_cdclk()
2137 int divider, fraction; in cnp_rawclk() local
2141 divider = 24000; in cnp_rawclk()
[all …]
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| H A D | intel_lvds.c | 60 int divider; member
177 pps->divider = (val & PP_REFERENCE_DIVIDER_MASK) >> in intel_lvds_pps_get_hw_state()
206 pps->divider, pps->port, pps->powerdown_on_reset); in intel_lvds_pps_get_hw_state()
226 val = pps->divider << PP_REFERENCE_DIVIDER_SHIFT; in intel_lvds_pps_init_hw()
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| H A D | intel_dpll_mgr.c | 1062 unsigned int divider) in skl_wrpll_try_divider() argument
1076 ctx->p = divider; in skl_wrpll_try_divider()
1084 ctx->p = divider; in skl_wrpll_try_divider()
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| H A D | intel_dsi.c | 1286 static u16 txclkesc(u32 divider, unsigned int us) in txclkesc() argument
1288 switch (divider) { in txclkesc()
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| H A D | intel_display.c | 180 int divider; in vlv_get_cck_clock() local
186 divider = val & CCK_FREQUENCY_VALUES; in vlv_get_cck_clock()
189 (divider << CCK_FREQUENCY_STATUS_SHIFT), in vlv_get_cck_clock()
192 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); in vlv_get_cck_clock()
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| /dragonfly/sys/dev/drm/radeon/ |
| H A D | r600_dpm.h | 179 u32 index, u32 divider);
181 u32 index, u32 divider);
183 u32 index, u32 divider);
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| H A D | trinity_dpm.c | 618 u32 index, u32 divider) in trinity_set_ds_dividers() argument
625 value |= DS_DIV(divider); in trinity_set_ds_dividers()
630 u32 index, u32 divider) in trinity_set_ss_dividers() argument
637 value |= DS_SH_DIV(divider); in trinity_set_ss_dividers()
1834 u32 divider; in trinity_convert_did_to_freq() local
1837 divider = did * 25; in trinity_convert_did_to_freq()
1839 divider = (did - 64) * 50 + 1600; in trinity_convert_did_to_freq()
1841 divider = (did - 96) * 100 + 3200; in trinity_convert_did_to_freq()
1843 divider = 128 * 100; in trinity_convert_did_to_freq()
1847 return ((pi->sys_info.dentist_vco_freq * 100) + (divider - 1)) / divider; in trinity_convert_did_to_freq()
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| H A D | radeon_legacy_crtc.c | 757 int divider; in radeon_set_pll() member
825 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { in radeon_set_pll()
826 if (post_div->divider == post_divider) in radeon_set_pll()
830 if (!post_div->divider) in radeon_set_pll()
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| H A D | sumo_dpm.c | 477 u32 index, u32 divider) in sumo_set_divider_value() argument
484 SCLK_FSTATE_0_DIV(divider), ~SCLK_FSTATE_0_DIV_MASK); in sumo_set_divider_value()
487 SCLK_FSTATE_1_DIV(divider), ~SCLK_FSTATE_1_DIV_MASK); in sumo_set_divider_value()
490 SCLK_FSTATE_2_DIV(divider), ~SCLK_FSTATE_2_DIV_MASK); in sumo_set_divider_value()
493 SCLK_FSTATE_3_DIV(divider), ~SCLK_FSTATE_3_DIV_MASK); in sumo_set_divider_value()
497 u32 index, u32 divider) in sumo_set_ds_dividers() argument
505 dpm_ctrl |= (divider << (index * 3)); in sumo_set_ds_dividers()
511 u32 index, u32 divider) in sumo_set_ss_dividers() argument
519 dpm_ctrl |= (divider << (index * 3)); in sumo_set_ss_dividers()
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| H A D | r600_dpm.c | 480 u32 index, u32 divider) in r600_engine_clock_entry_set_post_divider() argument
483 STEP_0_SPLL_POST_DIV(divider), ~STEP_0_SPLL_POST_DIV_MASK); in r600_engine_clock_entry_set_post_divider()
487 u32 index, u32 divider) in r600_engine_clock_entry_set_reference_divider() argument
490 STEP_0_SPLL_REF_DIV(divider), ~STEP_0_SPLL_REF_DIV_MASK); in r600_engine_clock_entry_set_reference_divider()
494 u32 index, u32 divider) in r600_engine_clock_entry_set_feedback_divider() argument
497 STEP_0_SPLL_FB_DIV(divider), ~STEP_0_SPLL_FB_DIV_MASK); in r600_engine_clock_entry_set_feedback_divider()
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| H A D | rv6xx_dpm.c | 381 u32 index, u32 divider) in rv6xx_memory_clock_entry_set_post_divider() argument
384 LEVEL0_MPLL_POST_DIV(divider), ~LEVEL0_MPLL_POST_DIV_MASK); in rv6xx_memory_clock_entry_set_post_divider()
388 u32 index, u32 divider) in rv6xx_memory_clock_entry_set_feedback_divider() argument
390 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), LEVEL0_MPLL_FB_DIV(divider), in rv6xx_memory_clock_entry_set_feedback_divider()
395 u32 index, u32 divider) in rv6xx_memory_clock_entry_set_reference_divider() argument
398 LEVEL0_MPLL_REF_DIV(divider), ~LEVEL0_MPLL_REF_DIV_MASK); in rv6xx_memory_clock_entry_set_reference_divider()
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| /dragonfly/usr.bin/units/ |
| H A D | units.c | 305 char *divider, *slash, *offset; in addunit() local
337 divider = strchr(item, '|'); in addunit()
338 if (divider) { in addunit()
339 *divider = 0; in addunit()
352 num = atof(divider + 1); in addunit()
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| /dragonfly/sys/dev/drm/amd/display/dc/inc/hw/ |
| H A D | opp.h | 238 uint32_t divider; /* (actually HW range is min/divider; divider !=0) */ member
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| /dragonfly/contrib/zstd/lib/compress/ |
| H A D | zstd_compress.c | 1308 U32 const divider = (cParams->minMatch==3) ? 3 : 4; in ZSTD_estimateCCtxSize_usingCCtxParams_internal() local
1309 size_t const maxNbSeq = blockSize / divider; in ZSTD_estimateCCtxSize_usingCCtxParams_internal()
1623 U32 const divider = (params.cParams.minMatch==3) ? 3 : 4; in ZSTD_resetCCtx_internal() local
1624 size_t const maxNbSeq = blockSize / divider; in ZSTD_resetCCtx_internal()
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| /dragonfly/share/dict/ |
| H A D | web2a | 7352 bow divider
20795 fertilizer divider
70451 voltage divider
73888 wing divider
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| H A D | web2 | 56274 divider
|