/qemu/tests/qtest/ |
H A D | stm32l4x5_gpio-test.c | 113 uint32_t offset = 2 * pin; in gpio_set_2bits() 329 gpio_set_irq(gpio, pin, 1); in test_gpio_input_mode() 334 gpio_set_irq(gpio, pin, 0); in test_gpio_input_mode() 388 gpio_set_irq(gpio, pin, 1); in test_push_pull() 395 gpio_set_irq(gpio2, pin, 0); in test_push_pull() 402 gpio_set_irq(gpio, pin, 1); in test_push_pull() 407 gpio_set_irq(gpio2, pin, 0); in test_push_pull() 435 gpio_set_irq(gpio, pin, 1); in test_open_drain() 452 gpio_set_irq(gpio, pin, 1); in test_open_drain() 458 gpio_set_irq(gpio, pin, 0); in test_open_drain() [all …]
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H A D | pnv-host-i2c-test.c | 166 static void pnv_i2c_pca9554_set_pin(PnvI2cDev *dev, int pin, bool high) in pnv_i2c_pca9554_set_pin() argument 170 uint8_t mask = 0x1 << pin; in pnv_i2c_pca9554_set_pin() 171 uint8_t new_value = ((high) ? 1 : 0) << pin; in pnv_i2c_pca9554_set_pin() 273 static void pnv_i2c_pca9552_set_pin(PnvI2cDev *dev, int pin, bool high) in pnv_i2c_pca9552_set_pin() argument 277 uint8_t reg = PCA9552_LS0 + (pin / 4); in pnv_i2c_pca9552_set_pin() 278 uint8_t shift = (pin % 4) * 2; in pnv_i2c_pca9552_set_pin()
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/qemu/hw/gpio/ |
H A D | pca9554.c | 155 int pin, rc; in pca9554_get_pin() local 158 rc = sscanf(name, "pin%2d", &pin); in pca9554_get_pin() 163 if (pin < 0 || pin >= PCA9554_PIN_COUNT) { in pca9554_get_pin() 170 state = (state >> pin) & 0x1; in pca9554_get_pin() 178 int pin, rc, val; in pca9554_set_pin() local 190 if (pin < 0 || pin >= PCA9554_PIN_COUNT) { in pca9554_set_pin() 207 mask = 0x1 << pin; in pca9554_set_pin() 253 int pin; in pca9554_initfn() local 255 for (pin = 0; pin < PCA9554_PIN_COUNT; pin++) { in pca9554_initfn() 268 s->ext_state[pin] = level; in pca9554_set_ext_state() [all …]
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H A D | stm32l4x5_gpio.c | 49 static bool is_pull_up(Stm32l4x5GpioState *s, unsigned pin) in is_pull_up() argument 51 return extract32(s->pupdr, 2 * pin, 2) == 1; in is_pull_up() 54 static bool is_pull_down(Stm32l4x5GpioState *s, unsigned pin) in is_pull_down() argument 56 return extract32(s->pupdr, 2 * pin, 2) == 2; in is_pull_down() 59 static bool is_output(Stm32l4x5GpioState *s, unsigned pin) in is_output() argument 61 return extract32(s->moder, 2 * pin, 2) == 1; in is_output() 66 return extract32(s->otyper, pin, 1) == 1; in is_open_drain() 69 static bool is_push_pull(Stm32l4x5GpioState *s, unsigned pin) in is_push_pull() argument 71 return extract32(s->otyper, pin, 1) == 0; in is_push_pull() 190 qemu_irq_raise(s->pin[i]); in update_gpio_idr() [all …]
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H A D | pca9552.c | 52 static uint8_t pca955x_pin_get_config(PCA955xState *s, int pin) in pca955x_pin_get_config() argument 54 uint8_t reg = PCA9552_LS0 + (pin / 4); in pca955x_pin_get_config() 55 uint8_t shift = (pin % 4) << 1; in pca955x_pin_get_config() 398 static void pca955x_set_ext_state(PCA955xState *s, int pin, int level) in pca955x_set_ext_state() argument 400 if (s->ext_state[pin] != level) { in pca955x_set_ext_state() 402 s->ext_state[pin] = level; in pca955x_set_ext_state() 408 static void pca955x_gpio_in_handler(void *opaque, int pin, int level) in pca955x_gpio_in_handler() argument 414 assert((pin >= 0) && (pin < k->pin_count)); in pca955x_gpio_in_handler() 415 pca955x_set_ext_state(s, pin, level); in pca955x_gpio_in_handler()
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H A D | aspeed_gpio.c | 321 uint32_t pin) in aspeed_gpio_get_pin_level() argument 324 uint32_t pin_mask = 1 << pin; in aspeed_gpio_get_pin_level() 335 uint32_t pin_mask = 1 << pin; in aspeed_gpio_set_pin_level() 903 int pin = 0xfff; in aspeed_gpio_get_pin() local 909 if (sscanf(name, "gpio%2[A-Z]%1d", group, &pin) != 2) { in aspeed_gpio_get_pin() 921 pin = pin + group_idx * GPIOS_PER_GROUP; in aspeed_gpio_get_pin() 922 level = aspeed_gpio_get_pin_level(s, set_idx, pin); in aspeed_gpio_get_pin() 930 int pin = 0xfff; in aspeed_gpio_set_pin() local 938 if (sscanf(name, "gpio%2[A-Z]%1d", group, &pin) != 2) { in aspeed_gpio_set_pin() 950 pin = pin + group_idx * GPIOS_PER_GROUP; in aspeed_gpio_set_pin() [all …]
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H A D | sifive_gpio.c | 25 uint32_t pin; in update_output_irq() local 33 pin = 1 << i; in update_output_irq() 34 qemu_set_irq(s->irq[i], (pending & pin) != 0); in update_output_irq() 35 trace_sifive_gpio_update_output_irq(i, (pending & pin) != 0); in update_output_irq()
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/qemu/hw/ppc/ |
H A D | ppc.c | 78 trace_ppc_irq_set(env, pin, level); in ppc6xx_set_irq() 85 switch (pin) { in ppc6xx_set_irq() 139 env->irq_input_state |= 1 << pin; in ppc6xx_set_irq() 158 trace_ppc_irq_set(env, pin, level); in ppc970_set_irq() 165 switch (pin) { in ppc970_set_irq() 234 switch (pin) { in power7_set_irq() 257 switch (pin) { in power9_set_irq() 347 trace_ppc_irq_set(env, pin, level); in ppc40x_set_irq() 354 switch (pin) { in ppc40x_set_irq() 422 trace_ppc_irq_set(env, pin, level); in ppce500_set_irq() [all …]
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/qemu/hw/intc/ |
H A D | mips_gic.c | 25 static void mips_gic_set_vp_irq(MIPSGICState *gic, int vp, int pin) in mips_gic_set_vp_irq() argument 32 if ((gic->irq_state[i].map_pin & GIC_MAP_MSK) == pin && in mips_gic_set_vp_irq() 42 if (((gic->vps[vp].compare_map & GIC_MAP_MSK) == pin) && in mips_gic_set_vp_irq() 50 pin + GIC_CPU_PIN_OFFSET, in mips_gic_set_vp_irq() 53 qemu_set_irq(gic->vps[vp].env->irq[pin + GIC_CPU_PIN_OFFSET], in mips_gic_set_vp_irq() 61 int pin = gic->irq_state[n_IRQ].map_pin & GIC_MAP_MSK; in gic_update_pin_for_irq() local 66 mips_gic_set_vp_irq(gic, vp, pin); in gic_update_pin_for_irq() 205 uint32_t pin = (gic->vps[vp_index].compare_map & GIC_MAP_MSK); in gic_timer_expire_cb() local 207 [pin + GIC_CPU_PIN_OFFSET]); in gic_timer_expire_cb() 217 uint32_t pin = (gic->vps[vp_index].compare_map & GIC_MAP_MSK); in gic_timer_store_vp_compare() local [all …]
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H A D | loongarch_extioi.c | 272 int i, pin; in loongarch_extioi_realize() local 294 for (pin = 0; pin < LS3A_INTC_IP; pin++) { in loongarch_extioi_realize() 295 qdev_init_gpio_out(dev, &s->cpu[i].parent_irq[pin], 1); in loongarch_extioi_realize()
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/qemu/hw/vfio/ |
H A D | platform.c | 68 intp->pin = info.index; in vfio_init_intp() 122 ret = vfio_set_irq_signaling(vbasedev, intp->pin, 0, in vfio_set_trigger_eventfd() 174 trace_vfio_platform_intp_mmap_enable(tmp->pin); in vfio_intp_mmap_enable() 196 trace_vfio_platform_intp_inject_pending_lockheld(intp->pin, in vfio_intp_inject_pending_lockheld() 236 trace_vfio_intp_interrupt_set_pending(intp->pin); in vfio_intp_interrupt() 243 trace_vfio_platform_intp_interrupt(intp->pin, in vfio_intp_interrupt() 295 trace_vfio_platform_eoi(intp->pin, in vfio_platform_eoi() 304 vfio_unmask_single_irqindex(vbasedev, intp->pin); in vfio_platform_eoi() 361 ret = vfio_set_irq_signaling(vbasedev, intp->pin, 0, in vfio_set_resample_eventfd() 407 trace_vfio_platform_start_level_irqfd_injection(intp->pin, in vfio_start_irqfd_injection() [all …]
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/qemu/hw/pci-host/ |
H A D | ppce500.c | 343 static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int pin) in mpc85xx_pci_map_irq() argument 348 ret = ppce500_pci_map_irq_slot(devno, pin); in mpc85xx_pci_map_irq() 351 pci_dev->devfn, pin, ret, devno); in mpc85xx_pci_map_irq() 356 static void mpc85xx_pci_set_irq(void *opaque, int pin, int level) in mpc85xx_pci_set_irq() argument 361 pci_debug("%s: PCI irq %d, level:%d\n", __func__, pin , level); in mpc85xx_pci_set_irq() 363 qemu_set_irq(pic[pin], level); in mpc85xx_pci_set_irq() 366 static PCIINTxRoute e500_route_intx_pin_to_irq(void *opaque, int pin) in e500_route_intx_pin_to_irq() argument 372 route.irq = s->irq_num[pin]; in e500_route_intx_pin_to_irq() 374 pci_debug("%s: PCI irq-pin = %d, irq_num= %d\n", __func__, pin, route.irq); in e500_route_intx_pin_to_irq()
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H A D | articia.c | 153 static int amigaone_pcihost_bus0_map_irq(PCIDevice *pdev, int pin) in amigaone_pcihost_bus0_map_irq() argument 161 return pin; in amigaone_pcihost_bus0_map_irq() 163 return pci_swizzle(devfn_slot, pin); in amigaone_pcihost_bus0_map_irq()
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H A D | gpex.c | 61 static PCIINTxRoute gpex_route_intx_pin_to_irq(void *opaque, int pin) in gpex_route_intx_pin_to_irq() argument 65 int gsi = s->irq_num[pin]; in gpex_route_intx_pin_to_irq()
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/qemu/hw/arm/ |
H A D | b-l475e-iot01a.c | 78 unsigned gpio, pin; in bl475e_init() local 106 pin = dm163_input[i] % GPIO_NUM_PINS; in bl475e_init() 107 qdev_connect_gpio_out(DEVICE(&s->soc.gpio[gpio]), pin, in bl475e_init()
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/qemu/docs/specs/ |
H A D | pci-serial.rst | 23 Wired to pin A. 37 Wired to pin A.
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/qemu/tests/tcg/hexagon/ |
H A D | hvx_misc.h | 100 void *pin = buffer0; \ 103 VEC_OP1(ASM, EL, pin, pout); \ 104 pin += sizeof(MMVector); \
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/qemu/hw/openrisc/ |
H A D | virt.c | 319 int pin, dev; in create_pcie_irq_map() local 336 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { in create_pcie_irq_map() 337 int irq_nr = irq_base + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); in create_pcie_irq_map() 346 irq_map[i++] = cpu_to_be32(pin + 1); in create_pcie_irq_map()
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/qemu/hw/loongarch/ |
H A D | virt.c | 370 int pin, dev; in fdt_add_pcie_irq_map_node() local 388 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { in fdt_add_pcie_irq_map_node() 389 int irq_nr = 16 + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); in fdt_add_pcie_irq_map_node() 397 irq_map[i] = cpu_to_be32(pin + 1); in fdt_add_pcie_irq_map_node() 672 int cpu, pin, i, start, num; in virt_irq_init() local 736 for (pin = 0; pin < LS3A_INTC_IP; pin++) { in virt_irq_init() 737 qdev_connect_gpio_out(extioi, (cpu * 8 + pin), in virt_irq_init() 738 qdev_get_gpio_in(cpudev, pin + 2)); in virt_irq_init()
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/qemu/hw/isa/ |
H A D | vt82c686.c | 641 static int via_isa_get_pci_irq(const ViaISAState *s, int pin) in via_isa_get_pci_irq() argument 643 switch (pin) { in via_isa_get_pci_irq() 656 void via_isa_set_irq(PCIDevice *d, int pin, int level) in via_isa_set_irq() argument 665 irq = via_isa_get_pci_irq(s, pin); in via_isa_set_irq() 666 f = 8 + pin; /* Use function 8-11 for PCI interrupt inputs */ in via_isa_set_irq() 702 static void via_isa_pirq(void *opaque, int pin, int level) in via_isa_pirq() argument 704 via_isa_set_irq(opaque, pin, level); in via_isa_pirq()
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/qemu/include/hw/pci/ |
H A D | pci.h | 267 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); 297 static inline int pci_swizzle(int slot, int pin) in pci_swizzle() argument 299 return (slot + pin) % PCI_NUM_PINS; in pci_swizzle() 301 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); 310 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
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/qemu/docs/system/arm/ |
H A D | stm32.rst | 20 ultra-low-power series. The STM32F4 series is pin-to-pin compatible with STM32F2 series.
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/qemu/hw/pci-bridge/ |
H A D | pci_expander_bridge.c | 260 static int pxb_map_irq_fn(PCIDevice *pci_dev, int pin) in pxb_map_irq_fn() argument 268 pin = pci_swizzle_map_irq_fn(pci_dev, pin); in pxb_map_irq_fn() 281 return pin - PCI_SLOT(pxb->devfn); in pxb_map_irq_fn()
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/qemu/include/hw/sensor/ |
H A D | tmp105.h | 38 qemu_irq pin; member
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/qemu/include/hw/gpio/ |
H A D | stm32l4x5_gpio.h | 68 qemu_irq pin[GPIO_NUM_PINS]; member
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