| /qemu/target/ppc/ |
| H A D | compat.c | 32 uint32_t pvr; member
53 .pvr = CPU_POWERPC_LOGICAL_2_05,
61 .pvr = CPU_POWERPC_LOGICAL_2_06,
69 .pvr = CPU_POWERPC_LOGICAL_2_06_PLUS,
77 .pvr = CPU_POWERPC_LOGICAL_2_07,
84 .pvr = CPU_POWERPC_LOGICAL_3_00,
98 .pvr = CPU_POWERPC_LOGICAL_3_10,
105 static const CompatInfo *compat_by_pvr(uint32_t pvr) in compat_by_pvr() argument
110 if (compat_table[i].pvr == pvr) { in compat_by_pvr()
311 compat_pvr = compat->pvr; in ppc_compat_prop_set()
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| H A D | cpu_init.c | 6380 if ((pvr & 0x0f00) != (pcc->pvr & 0x0f00)) { in ppc_pvr_match_power9()
6385 if ((pvr & 0x0f00) == 0x200) { in ppc_pvr_match_power9()
6386 if ((pvr & 0xf) < 2) { in ppc_pvr_match_power9()
6569 if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) { in ppc_pvr_match_power10()
6891 uint32_t pvr = *(uint32_t *)b; in ppc_cpu_compare_class_pvr() local
6900 return pcc->pvr == pvr ? 0 : -1; in ppc_cpu_compare_class_pvr()
6921 uint32_t pvr = *(uint32_t *)b; in ppc_cpu_compare_class_pvr_mask() local
6970 unsigned long pvr; in ppc_cpu_class_by_name() local
7042 if (pcc_a->pvr < pcc_b->pvr) { in ppc_cpu_list_compare()
7044 } else if (pcc_a->pvr > pcc_b->pvr) { in ppc_cpu_list_compare()
[all …]
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| H A D | machine.c | 234 static bool pvr_match(PowerPCCPU *cpu, uint32_t pvr) in pvr_match() argument
238 if (pvr == pcc->pvr) { in pvr_match()
241 return pcc->pvr_match(pcc, pvr, true); in pvr_match()
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| H A D | cpu-models.c | 33 #define POWERPC_DEF_PREFIX(pvr, svr, type) \ argument
34 glue(glue(glue(glue(pvr, _), svr), _), type)
43 pcc->pvr = _pvr; \
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| H A D | kvm.c | 207 sregs.pvr = cenv->spr[SPR_PVR]; in kvm_arch_sync_sregs()
865 sregs.pvr = env->spr[SPR_PVR]; in kvmppc_put_books_sregs()
2335 uint32_t pvr; in mfpvr() local
2338 : "=r"(pvr)); in mfpvr()
2339 return pvr; in mfpvr()
2358 pcc->pvr = mfpvr(); in kvmppc_host_cpu_class_init()
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| H A D | cpu.h | 1472 uint32_t pvr; member
1477 bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr, bool best);
1504 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1505 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
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| H A D | helper_regs.c | 450 pcc->pvr); in register_generic_sprs()
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| /qemu/target/sh4/ |
| H A D | cpu.c | 170 scc->pvr = 0x00050000; in sh7750r_class_init()
187 scc->pvr = 0x04050005; in sh7751r_class_init()
204 scc->pvr = 0x10300700; in sh7785_class_init()
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| H A D | cpu.h | 238 uint32_t pvr; member
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| /qemu/hw/ppc/ |
| H A D | spapr_hcall.c | 1124 uint32_t pvr, pvr_mask; in cas_check_pvr() local
1127 pvr = ldl_be_phys(&address_space_memory, *addr + 4); in cas_check_pvr()
1130 if (~pvr_mask & pvr) { in cas_check_pvr()
1134 if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { in cas_check_pvr()
1137 if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { in cas_check_pvr()
1138 best_compat = pvr; in cas_check_pvr()
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| H A D | pnv.c | 833 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); in pnv_match_cpu()
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| /qemu/pc-bios/ |
| H A D | petalogix-s3adsp1800.dts | 89 xlnx,pvr = <0x01>;
90 xlnx,pvr-user1 = <0x00>;
91 xlnx,pvr-user2 = <0x00>;
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| H A D | petalogix-ml605.dts | 109 xlnx,pvr = < 0x02 >;
110 xlnx,pvr-user1 = < 0x00 >;
111 xlnx,pvr-user2 = < 0x00 >;
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| /qemu/target/microblaze/ |
| H A D | cpu.c | 267 (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) | in mb_cpu_realizefn()
387 DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
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| H A D | cpu.h | 314 uint8_t pvr; member
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| /qemu/linux-headers/asm-powerpc/ |
| H A D | kvm.h | 176 __u32 pvr; member
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| /qemu/hw/sh4/ |
| H A D | sh7750.c | 303 return scc->pvr; in sh7750_mem_readl()
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| /qemu/tests/data/qobject/ |
| H A D | qdict.txt | 3409 cpuinfo-pvr-full.c: 2822
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