/qemu/target/hppa/ |
H A D | gdbstub.c | 73 val = env->sr[4] >> 32; in hppa_cpu_gdb_read_register() 76 val = env->sr[0] >> 32; in hppa_cpu_gdb_read_register() 79 val = env->sr[1] >> 32; in hppa_cpu_gdb_read_register() 82 val = env->sr[2] >> 32; in hppa_cpu_gdb_read_register() 85 val = env->sr[3] >> 32; in hppa_cpu_gdb_read_register() 88 val = env->sr[5] >> 32; in hppa_cpu_gdb_read_register() 91 val = env->sr[6] >> 32; in hppa_cpu_gdb_read_register() 94 val = env->sr[7] >> 32; in hppa_cpu_gdb_read_register() 199 env->sr[4] = (uint64_t)val << 32; in hppa_cpu_gdb_write_register() 202 env->sr[0] = (uint64_t)val << 32; in hppa_cpu_gdb_write_register() [all …]
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H A D | cpu.c | 87 if ((env->sr[4] == env->sr[5]) in cpu_get_tb_cpu_state() 88 & (env->sr[4] == env->sr[6]) in cpu_get_tb_cpu_state() 89 & (env->sr[4] == env->sr[7])) { in cpu_get_tb_cpu_state()
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/qemu/tests/tcg/xtensa/ |
H A D | test_sr.S | 3 test_suite sr 17 .macro sr_op sym, op_sym, op_byte, sr 19 \op_sym a4, \sr 21 .byte LOW__SR, \sr, \op_byte 25 .macro test_sr_op sym, mask, op, op_byte, sr 29 sr_op \sym, \op, \op_byte, \sr 33 sr_op \sym, \op, \op_byte, \sr 45 .macro test_sr_mask sr, sym, mask 46 test \sr 53 .macro test_sr sr, conf [all …]
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H A D | fpu.h | 49 .macro test_op1_rm op, fr0, fr1, v0, r, sr 54 check_res \fr1, \r, \sr 57 .macro test_op2_rm op, fr0, fr1, fr2, v0, v1, r, sr 63 check_res \fr2, \r, \sr 73 check_res \fr3, \r, \sr 76 .macro test_op1_ex op, fr0, fr1, v0, rm, r, sr 79 test_op1_rm \op, \fr0, \fr1, \v0, \r, \sr 82 test_op1_rm \op, \fr0, \fr1, \v0, \r, \sr 85 .macro test_op2_ex op, fr0, fr1, fr2, v0, v1, rm, r, sr 88 test_op2_rm \op, \fr0, \fr1, \fr2, \v0, \v1, \r, \sr [all …]
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H A D | test_fp0_conv.S | 13 .macro test_ftoi_ex op, r0, fr0, v, c, r, sr 23 movi a3, \sr 30 .macro test_ftoi op, r0, fr0, v, c, r, sr 33 test_ftoi_ex \op, \r0, \fr0, \v, \c, \r, \sr 36 test_ftoi_ex \op, \r0, \fr0, \v, \c, \r, \sr 40 .macro test_itof_ex op, fr0, ar0, v, c, r, sr 52 movi a3, \sr 59 .macro test_itof_rm op, fr0, ar0, v, c, rm, r, sr 62 test_itof_ex \op, \fr0, \ar0, \v, \c, \r, \sr 65 test_itof_ex \op, \fr0, \ar0, \v, \c, \r, \sr [all …]
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H A D | test_fp1.S | 13 .macro test_ord_ex op, br, fr0, fr1, v0, v1, r, sr 25 movi a3, \sr 32 .macro test_ord op, br, fr0, fr1, v0, v1, r, sr 35 test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r, \sr 38 test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r, \sr
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/qemu/hw/i2c/ |
H A D | mpc_i2c.c | 83 uint8_t sr; member 105 return s->sr & CSR_MIF; in mpc_i2c_irq_pending() 121 i2c->sr = 0x81; in mpc_i2c_reset() 153 s->sr |= CSR_RXAK; in mpc_i2c_address_send() 156 s->sr &= ~CSR_RXAK; in mpc_i2c_address_send() 167 s->sr |= CSR_RXAK; in mpc_i2c_data_send() 170 s->sr &= ~CSR_RXAK; in mpc_i2c_data_send() 209 value = s->sr; in mpc_i2c_read() 255 s->sr |= CSR_MBB; in mpc_i2c_write() 258 s->sr &= ~CSR_MBB; in mpc_i2c_write() [all …]
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/qemu/hw/char/ |
H A D | mcf_uart.c | 25 uint8_t sr; member 72 if (s->sr & MCF_UART_TxRDY) in OBJECT_DECLARE_SIMPLE_TYPE() 89 return s->sr; in mcf_uart_read() 130 s->sr |= MCF_UART_TxEMP; in mcf_uart_do_tx() 133 s->sr |= MCF_UART_TxRDY; in mcf_uart_do_tx() 135 s->sr &= ~MCF_UART_TxRDY; in mcf_uart_do_tx() 155 s->sr |= MCF_UART_TxEMP; in mcf_do_command() 156 s->sr &= ~MCF_UART_TxRDY; in mcf_do_command() 240 s->sr = MCF_UART_TxEMP; in mcf_uart_reset() 255 s->sr |= MCF_UART_RxRDY; in mcf_uart_push_byte() [all …]
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H A D | ipoctal232.c | 106 uint8_t sr; member 235 ch->sr &= ~SR_RXRDY; in write_cr() 284 ret = ch->sr; in io_read() 294 ch->sr &= ~SR_RXRDY; in io_read() 300 if (ch->sr & SR_BREAK) { in io_read() 301 ch->sr &= ~SR_BREAK; in io_read() 362 if (ch->sr & SR_TXRDY) { in io_write() 494 if (!(ch->sr & SR_RXRDY)) { in hostdev_receive() 502 ch->sr |= SR_RXRDY; in hostdev_receive() 518 if (!(ch->sr & SR_BREAK)) { in hostdev_event() [all …]
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/qemu/target/openrisc/ |
H A D | interrupt.c | 47 env->sr &= ~SR_DME; in openrisc_cpu_do_interrupt() 48 env->sr &= ~SR_IME; in openrisc_cpu_do_interrupt() 49 env->sr |= SR_SM; in openrisc_cpu_do_interrupt() 50 env->sr &= ~SR_IEE; in openrisc_cpu_do_interrupt() 51 env->sr &= ~SR_TEE; in openrisc_cpu_do_interrupt() 59 env->sr |= SR_DSX; in openrisc_cpu_do_interrupt() 62 env->sr &= ~SR_DSX; in openrisc_cpu_do_interrupt() 94 if (env->sr & SR_EPH) { in openrisc_cpu_do_interrupt() 110 if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->sr & SR_IEE)) { in openrisc_cpu_exec_interrupt() 113 if ((interrupt_request & CPU_INTERRUPT_TIMER) && (env->sr & SR_TEE)) { in openrisc_cpu_exec_interrupt()
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H A D | mmu.c | 145 int prot, excp, sr = cpu->env.sr; in openrisc_cpu_get_phys_page_debug() local 148 switch (sr & (SR_DME | SR_IME)) { in openrisc_cpu_get_phys_page_debug() 153 (sr & SR_SM) != 0); in openrisc_cpu_get_phys_page_debug() 159 (sr & SR_SM) != 0); in openrisc_cpu_get_phys_page_debug() 168 (sr & SR_SM) != 0); in openrisc_cpu_get_phys_page_debug()
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/qemu/target/ppc/ |
H A D | mmu-hash32.c | 96 key = !!(mmuidx_pr(mmu_idx) ? (sr & SR32_KP) : (sr & SR32_KS)); in ppc_hash32_pte_prot() 99 return ppc_hash32_pp_prot(key, pp, !!(sr & SR32_NX)); in ppc_hash32_pte_prot() 199 int key = !!(mmuidx_pr(mmu_idx) ? (sr & SR32_KP) : (sr & SR32_KS)); in ppc_hash32_direct_store() 344 vsid = sr & SR32_VSID; in ppc_hash32_htab_lookup() 391 target_ulong sr; in ppc_hash32_xlate() local 439 sr = env->sr[eaddr >> 28]; in ppc_hash32_xlate() 442 if (sr & SR32_T) { in ppc_hash32_xlate() 448 if (access_type == MMU_INST_FETCH && (sr & SR32_NX)) { in ppc_hash32_xlate() 457 pte_offset = ppc_hash32_htab_lookup(cpu, sr, eaddr, &pte); in ppc_hash32_xlate() 481 prot = ppc_hash32_pte_prot(mmu_idx, sr, pte); in ppc_hash32_xlate() [all …]
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H A D | mmu_common.c | 374 target_ulong sr, pgidx; in get_segment_6xx_tlb() local 379 sr = env->sr[eaddr >> 28]; in get_segment_6xx_tlb() 382 ds = sr & 0x80000000 ? 1 : 0; in get_segment_6xx_tlb() 384 vsid = sr & 0x00FFFFFF; in get_segment_6xx_tlb() 1080 target_ulong sr; in mmu6xx_dump_mmu() local 1088 sr = env->sr[i]; in mmu6xx_dump_mmu() 1089 if (sr & 0x80000000) { in mmu6xx_dump_mmu() 1092 sr & 0x80000000 ? 1 : 0, sr & 0x40000000 ? 1 : 0, in mmu6xx_dump_mmu() 1093 sr & 0x20000000 ? 1 : 0, (uint32_t)((sr >> 20) & 0x1FF), in mmu6xx_dump_mmu() 1097 sr & 0x80000000 ? 1 : 0, sr & 0x40000000 ? 1 : 0, in mmu6xx_dump_mmu() [all …]
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/qemu/target/m68k/ |
H A D | op_helper.c | 47 uint16_t sr; in m68k_rte() local 191 uint32_t sr; in cf_interrupt_all() local 213 sr = env->sr | cpu_m68k_get_ccr(env); in cf_interrupt_all() 223 fmt |= sr; in cf_interrupt_all() 225 env->sr |= SR_S; in cf_interrupt_all() 227 env->sr = (env->sr & ~SR_I) | (env->pending_level << SR_I_SHIFT); in cf_interrupt_all() 293 sr = env->sr | cpu_m68k_get_ccr(env); in m68k_interrupt_all() 306 oldsr = sr; in m68k_interrupt_all() 308 sr |= SR_S; in m68k_interrupt_all() 310 sr &= ~SR_T; in m68k_interrupt_all() [all …]
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/qemu/hw/ssi/ |
H A D | pl022.c | 53 s->sr = 0; in pl022_update() 55 s->sr |= PL022_SR_TFE; in pl022_update() 57 s->sr |= PL022_SR_TNF; in pl022_update() 59 s->sr |= PL022_SR_RNE; in pl022_update() 61 s->sr |= PL022_SR_RFF; in pl022_update() 63 s->sr |= PL022_SR_BSY; in pl022_update() 143 return s->sr; in pl022_read() 225 s->sr = PL022_SR_TFE | PL022_SR_TNF; in pl022_reset() 256 VMSTATE_UINT32(sr, PL022State),
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/qemu/target/sh4/ |
H A D | cpu.h | 145 uint32_t sr; /* status register (with T split out) */ member 370 return env->sr | (env->sr_m << SR_M) | in cpu_read_sr() 375 static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr) in cpu_write_sr() argument 377 env->sr_m = (sr >> SR_M) & 1; in cpu_write_sr() 378 env->sr_q = (sr >> SR_Q) & 1; in cpu_write_sr() 379 env->sr_t = (sr >> SR_T) & 1; in cpu_write_sr() 380 env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T)); in cpu_write_sr() 391 | (env->sr & TB_FLAG_SR_MASK) in cpu_get_tb_cpu_state()
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H A D | gdbstub.c | 33 if ((env->sr & (1u << SR_MD)) && (env->sr & (1u << SR_RB))) { in superh_cpu_gdb_read_register() 82 if ((env->sr & (1u << SR_MD)) && (env->sr & (1u << SR_RB))) { in superh_cpu_gdb_write_register()
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H A D | helper.c | 68 if (env->sr & (1u << SR_BL)) { in superh_cpu_do_interrupt() 87 (env->sr >> 4) & 0xf); in superh_cpu_do_interrupt() 147 env->sr |= (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB); in superh_cpu_do_interrupt() 163 env->sr &= ~(1u << SR_FD); in superh_cpu_do_interrupt() 164 env->sr |= 0xf << 4; /* IMASK */ in superh_cpu_do_interrupt() 334 use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD)); in get_mmu_address() 340 if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) { in get_mmu_address() 368 if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) { in get_mmu_address() 400 if (!(env->sr & (1u << SR_MD)) in get_physical_address() 610 int use_asid = !(s->mmucr & MMUCR_SV) || !(s->sr & (1u << SR_MD)); in cpu_sh4_write_mmaped_utlb_addr() [all …]
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/qemu/hw/audio/ |
H A D | ac97.c | 112 uint16_t sr; /* rw 1 */ member 223 r->sr = new_sr; in update_sr() 226 r->sr & SR_BCIS, r->sr & SR_LVBCI, r->sr, event, level); in update_sr() 694 val = r->sr & 0xff; in nabm_readb() 715 val = r->sr; in nabm_readw() 752 r->civ, r->lvi, r->sr); in nabm_readl() 792 r->sr &= ~(SR_DCH | SR_CELV); in nabm_writeb() 810 r->sr |= SR_DCH; in nabm_writeb() 815 r->sr &= ~SR_DCH; in nabm_writeb() 1005 if (r->sr & SR_DCH) { in transfer_audio() [all …]
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/qemu/hw/display/ |
H A D | cirrus_vga.c | 1156 if ((s->vga.sr[0x07] & 0x01) != 0) { in cirrus_get_bpp() 1274 return s->vga.sr[0x10]; in cirrus_vga_read_sr() 1283 return s->vga.sr[0x11]; in cirrus_vga_read_sr() 1347 s->vga.sr[0x10] = val; in cirrus_vga_write_sr() 1358 s->vga.sr[0x11] = val; in cirrus_vga_write_sr() 1391 s->vga.sr[0x12] = val; in cirrus_vga_write_sr() 1399 s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38) in cirrus_vga_write_sr() 2800 s->vga.sr[0x06] = 0x0f; in cirrus_reset() 2805 s->vga.sr[0x0f] = 0x98; in cirrus_reset() 2806 s->vga.sr[0x17] = 0x20; in cirrus_reset() [all …]
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H A D | vga.c | 135 static inline uint8_t sr(VGACommonState *s, int idx) in sr() function 137 return vbe_enabled(s) ? s->sr_vbe[idx] : s->sr[idx]; in sr() 225 clocking_mode = (sr(s, VGA_SEQ_CLOCK_MODE) >> 3) & 1; in vga_precise_update_retrace_info() 359 val = s->sr[s->sr_index]; in vga_ioport_read() 902 mask = sr(s, VGA_SEQ_PLANE_WRITE); in vga_mem_writeb() 1166 if (sr(s, VGA_SEQ_CLOCK_MODE) & 0x08) { in vga_get_text_resolution() 1208 v = sr(s, VGA_SEQ_CHARACTER_MAP); in vga_draw_text() 1525 if (sr(s, VGA_SEQ_CLOCK_MODE) & 8) { in vga_draw_graphic() 1535 if (sr(s, VGA_SEQ_CLOCK_MODE) & 8) { in vga_draw_graphic() 1827 memset(s->sr, '\0', sizeof(s->sr)); in vga_common_reset() [all …]
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/qemu/hw/nvme/ |
H A D | dif.c | 124 dif->g64.sr[0] = *reftag >> 40; in nvme_dif_pract_generate_dif_crc64() 125 dif->g64.sr[1] = *reftag >> 32; in nvme_dif_pract_generate_dif_crc64() 126 dif->g64.sr[2] = *reftag >> 24; in nvme_dif_pract_generate_dif_crc64() 127 dif->g64.sr[3] = *reftag >> 16; in nvme_dif_pract_generate_dif_crc64() 128 dif->g64.sr[4] = *reftag >> 8; in nvme_dif_pract_generate_dif_crc64() 129 dif->g64.sr[5] = *reftag; in nvme_dif_pract_generate_dif_crc64() 219 r |= (uint64_t)dif->g64.sr[0] << 40; in nvme_dif_prchk_crc64() 220 r |= (uint64_t)dif->g64.sr[1] << 32; in nvme_dif_prchk_crc64() 221 r |= (uint64_t)dif->g64.sr[2] << 24; in nvme_dif_prchk_crc64() 223 r |= (uint64_t)dif->g64.sr[4] << 8; in nvme_dif_prchk_crc64() [all …]
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/qemu/hw/timer/ |
H A D | imx_epit.c | 70 if ((s->sr & SR_OCIF) && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) { in imx_epit_update_int() 98 s->sr = 0; in imx_epit_reset() 129 reg_value = s->sr; in imx_epit_read() 289 s->sr = 0; /* SR.OCIF is the only bit in this register anyway */ in imx_epit_write_sr() 365 DPRINTF("sr was %d\n", s->sr); in imx_epit_cmp() 367 s->sr |= SR_OCIF; in imx_epit_cmp() 388 VMSTATE_UINT32(sr, IMXEPITState),
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H A D | imx_gpt.c | 69 VMSTATE_UINT32(sr, IMXGPTState), 157 if ((s->sr & s->ir) && (s->cr & GPT_CR_EN)) { in imx_gpt_update_int() 249 s->sr |= s->next_int; in imx_gpt_compute_next_timeout() 278 reg_value = s->sr; in imx_gpt_read() 343 s->sr = 0; in imx_gpt_reset_common() 427 s->sr &= ~(value & 0x3f); in imx_gpt_write() 490 s->sr |= s->next_int; in imx_gpt_timeout()
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/qemu/hw/sensor/ |
H A D | lsm303dlhc_mag.c | 62 uint8_t sr; member 237 s->sr = 0x3; in lsm303dlhc_mag_read() 259 s->sr = 0x1; in lsm303dlhc_mag_finish() 282 s->sr = s->buf; in lsm303dlhc_mag_write() 358 resp = s->sr; in lsm303dlhc_mag_recv() 460 VMSTATE_UINT8(sr, LSM303DLHCMagState), 488 s->sr = 0x1; /* DRDY = 1. */ in lsm303dlhc_mag_default_cfg()
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