/qemu/system/ |
H A D | meson.build | 14 'cpu-timers.c',
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/qemu/ |
H A D | MAINTAINERS | 3099 F: system/cpu-timers.c
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/qemu/docs/system/ |
H A D | target-sparc.rst | 45 - Slave I/O: timers, interrupt controllers, Zilog serial ports,
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H A D | gdb.rst | 199 the single step, but not timers, you would use:
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/qemu/hw/misc/ |
H A D | mac_via.c | 1217 ms->timers[0].frequency = VIA_TIMER_FREQ; in mos6522_q800_via1_reset_hold() 1218 ms->timers[1].frequency = VIA_TIMER_FREQ; in mos6522_q800_via1_reset_hold() 1371 ms->timers[0].frequency = VIA_TIMER_FREQ; in mos6522_q800_via2_reset_hold() 1372 ms->timers[1].frequency = VIA_TIMER_FREQ; in mos6522_q800_via2_reset_hold()
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H A D | mos6522.c | 433 s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; in mos6522_write() 438 s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); in mos6522_write() 440 set_counter(s, &s->timers[0], s->timers[0].latch); in mos6522_write() 443 s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; in mos6522_write() 448 s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); in mos6522_write() 454 s->timers[1].latch = (s->timers[1].latch & 0xff00) | val; in mos6522_write() 460 s->timers[1].latch = (s->timers[1].latch & 0xff) | (val << 8); in mos6522_write() 462 set_counter(s, &s->timers[1], s->timers[1].latch); in mos6522_write() 661 s->timers[0].latch = 0xffff; in mos6522_reset_hold() 666 s->timers[1].latch = 0xffff; in mos6522_reset_hold() [all …]
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/qemu/hw/misc/macio/ |
H A D | cuda.c | 598 ms->timers[0].frequency = CUDA_TIMER_FREQ; in mos6522_cuda_reset_hold() 599 ms->timers[1].frequency = (SCALE_US * 6000) / 4700; in mos6522_cuda_reset_hold()
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H A D | pmu.c | 806 ms->timers[0].frequency = VIA_TIMER_FREQ; in mos6522_pmu_reset_hold() 807 ms->timers[1].frequency = (SCALE_US * 6000) / 4700; in mos6522_pmu_reset_hold()
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/qemu/tests/unit/ |
H A D | test-throttle.c | 172 g_assert(tt->timers[THROTTLE_READ]); in test_init() 173 g_assert(tt->timers[THROTTLE_WRITE]); in test_init() 204 g_assert(tt->timers[THROTTLE_READ]); in test_init_readonly() 205 g_assert(!tt->timers[THROTTLE_WRITE]); in test_init_readonly() 236 g_assert(!tt->timers[THROTTLE_READ]); in test_init_writeonly() 237 g_assert(tt->timers[THROTTLE_WRITE]); in test_init_writeonly() 259 g_assert(!tt->timers[i]); in test_destroy()
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/qemu/qapi/ |
H A D | net.json | 897 # Parameters for self-announce timers 911 # @id: A name to be used to identify an instance of announce-timers
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/qemu/hw/timer/ |
H A D | grlib_gptimer.c | 87 GPTimer *timers; member 222 value = unit->timers[id].reload; in grlib_gptimer_read() 228 return unit->timers[id].config; in grlib_gptimer_read() 283 unit->timers[id].counter = value; in grlib_gptimer_write() 284 grlib_gptimer_enable(&unit->timers[id]); in grlib_gptimer_write() 290 unit->timers[id].reload = value; in grlib_gptimer_write() 304 unit->timers[id].config = value; in grlib_gptimer_write() 319 unit->timers[id].config = value; in grlib_gptimer_write() 359 GPTimer *timer = &unit->timers[i]; in grlib_gptimer_reset() 381 unit->timers = g_malloc0(sizeof unit->timers[0] * unit->nr_timers); in grlib_gptimer_realize() [all …]
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H A D | aspeed_timer.c | 64 const AspeedTimer (*timers)[] = (void *)t - (t->id * sizeof(*t)); in timer_to_ctrl() local 65 return container_of(timers, AspeedTimerCtrlState, timers); in timer_to_ctrl() 253 value = aspeed_timer_get_value(&s->timers[(offset >> 4)], reg); in aspeed_timer_read() 256 value = aspeed_timer_get_value(&s->timers[(offset >> 4) - 1], reg); in aspeed_timer_read() 273 t = &s->timers[timer]; in aspeed_timer_set_value() 406 t = &s->timers[i]; in aspeed_timer_set_ctrl() 596 AspeedTimer *t = &s->timers[id]; in aspeed_init_one_timer() 612 sysbus_init_irq(sbd, &s->timers[i].irq); in aspeed_timer_realize() 625 AspeedTimer *t = &s->timers[i]; in aspeed_timer_reset() 667 VMSTATE_STRUCT_ARRAY(timers, AspeedTimerCtrlState,
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H A D | mss-timer.c | 105 st = &t->timers[timer]; in timer_read() 154 st = &t->timers[timer]; in timer_write() 233 struct Msf2Timer *st = &t->timers[i]; in mss_timer_init() 253 struct Msf2Timer *st = &t->timers[i]; in mss_timer_finalize() 276 VMSTATE_STRUCT_ARRAY(timers, MSSTimerState, NUM_TIMERS, 0,
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H A D | xilinx_timer.c | 76 struct xlx_timer *timers; member 96 csr = t->timers[i].regs[R_TCSR]; in timer_update_irq() 114 xt = &t->timers[timer]; in timer_read() 165 xt = &t->timers[timer]; in timer_write() 220 t->timers = g_malloc0(sizeof t->timers[0] * num_timers(t)); in xilinx_timer_realize() 222 struct xlx_timer *xt = &t->timers[i]; in xilinx_timer_realize()
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/qemu/hw/net/ |
H A D | trace-events | 233 e1000e_irq_fire_all_timers(uint32_t val) "Firing all delay/throttling timers on all interrupts enab…
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/qemu/docs/system/i386/ |
H A D | xen.rst | 144 accelerated Xen PV timers and inter-processor interrupts (IPIs).
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/qemu/hw/intc/ |
H A D | openpic.c | 774 opp->timers[idx].tccr = val & ~TCCR_TOG; in openpic_tmr_write() 776 openpic_tmr_set_tmr(&opp->timers[idx], in openpic_tmr_write() 780 opp->timers[idx].tbcr = val; in openpic_tmr_write() 813 retval = opp->timers[idx].tbcr; in openpic_tmr_read() 1307 opp->timers[i].tccr = 0; in openpic_reset() 1308 opp->timers[i].tbcr = TBCR_CI; in openpic_reset() 1309 if (opp->timers[i].qemu_timer_active) { in openpic_reset() 1311 opp->timers[i].qemu_timer_active = false; in openpic_reset() 1365 opp->timers[i].n_IRQ = opp->irq_tim0 + i; in fsl_common_init() 1366 opp->timers[i].qemu_timer_active = false; in fsl_common_init() [all …]
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H A D | riscv_aclint.c | 109 timer_mod(mtimer->timers[hartid], next); in riscv_aclint_mtimer_write_timecmp() 292 s->timers = g_new0(QEMUTimer *, s->num_harts); in riscv_aclint_mtimer_realize() 392 s->timers[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL, in riscv_aclint_mtimer_create()
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/qemu/docs/devel/ |
H A D | replay.rst | 66 in sequence (e.g. expiring timers and checkpoints in the main thread 87 from timers, asynchronous input-output, and bottom halves. 89 Invocations of timers are coupled with clock reads and changing the state 98 QEMU in replay mode will try to invoke timers processing in random moment 99 of time. That's why we do not process a group of timers until the checkpoint 130 at the specified moments of time. There are several kinds of timers: 134 clock and timers does not affect deterministic replay at all. 135 * Virtual clock. These timers run only during the emulation. In icount 147 All virtual devices should use virtual clock for timers that change the guest 148 state. Virtual clock is deterministic, therefore such timers are deterministic [all …]
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/qemu/docs/system/arm/ |
H A D | vexpress.rst | 21 - SP804 timers
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/qemu/block/ |
H A D | throttle-groups.c | 346 timer_mod(tt->timers[direction], now); in schedule_next_request() 441 assert(!timer_pending(tgm->throttle_timers.timers[direction])); in throttle_group_restart_queue() 455 QEMUTimer *t = tgm->throttle_timers.timers[dir]; in throttle_group_restart_tgm() 604 assert(!timer_pending(tgm->throttle_timers.timers[dir])); in throttle_group_unregister_tgm() 647 if (timer_pending(tt->timers[dir])) { in throttle_group_detach_aio_context()
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/qemu/util/ |
H A D | throttle.c | 207 tt->timers[dir] = in throttle_timers_attach_aio_context() 269 throttle_timer_destroy(&tt->timers[dir]); in throttle_timers_detach_aio_context() 285 if (tt->timers[dir]) { in throttle_timers_are_initialized() 442 timer = tt->timers[direction]; in throttle_schedule_timer()
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/qemu/include/hw/ppc/ |
H A D | openpic.h | 165 OpenPICTimer timers[OPENPIC_MAX_TMR]; member
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/qemu/include/qemu/ |
H A D | throttle.h | 109 QEMUTimer *timers[THROTTLE_MAX]; /* timers used to do the throttling */ member
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/qemu/include/hw/misc/ |
H A D | mos6522.h | 146 MOS6522Timer timers[2]; member
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