Searched refs:CTTZ (Results 26 – 33 of 33) sorted by relevance
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1083 setOperationAction(ISD::CTTZ, VT, Expand); in AArch64TargetLowering()
1128 setOperationAction(ISD::CTTZ, VT, Custom); in AArch64TargetLowering()
1288 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom); in AArch64TargetLowering()
1328 setOperationAction(ISD::CTTZ, VT, Custom); in AArch64TargetLowering()
1467 setOperationAction(ISD::CTTZ, VT, Custom); in addTypeForFixedLengthSVE()
4709 case ISD::CTTZ: in LowerOperation()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 133 setOperationAction(ISD::CTTZ, VT, Expand); in M68kTargetLowering()
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 434 def cttz : SDNode<"ISD::CTTZ" , SDTIntBitCountUnaryOp>;
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 1661 case ISD::CTTZ: return visitCTTZ(N); in visit()
4207 SDValue C1 = DAG.getNode(ISD::CTTZ, DL, VT, N1); in visitSDIVLike()
9129 return DAG.getNode(ISD::CTTZ, SDLoc(N), VT, N0); in visitCTTZ()
22418 if ((Count.getOpcode() == ISD::CTTZ || in SimplifySelectCC()
22421 (!LegalOperations || TLI.isOperationLegal(ISD::CTTZ, VT))) in SimplifySelectCC()
22422 return DAG.getNode(ISD::CTTZ, DL, VT, N0); in SimplifySelectCC()
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| H A D | SelectionDAGBuilder.cpp | 6382 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF, in visitIntrinsicCall()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 205 setOperationAction(ISD::CTTZ, VT, Expand); in SystemZTargetLowering()
374 setOperationAction(ISD::CTTZ, VT, Legal); in SystemZTargetLowering()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 370 setOperationPromotedToType(ISD::CTTZ , MVT::i8 , MVT::i32); in X86TargetLowering()
378 setOperationAction(ISD::CTTZ, MVT::i16, Custom); in X86TargetLowering()
379 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); in X86TargetLowering()
383 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); in X86TargetLowering()
841 setOperationAction(ISD::CTTZ, VT, Expand); in X86TargetLowering()
27308 assert(!VT.isVector() && Op.getOpcode() == ISD::CTTZ && in LowerCTTZ()
30355 case ISD::CTTZ: in LowerOperation()
42772 Add.getOperand(0).getOpcode() == ISD::CTTZ) && in combineCMov()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 515 setOperationAction(ISD::CTTZ, MVT::i16, Promote); in SITargetLowering()
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