/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32F4xx_StdPeriph_Driver/src/ |
H A D | stm32f4xx_pwr.c | 58 #define CR_OFFSET (PWR_OFFSET + 0x00) macro 60 #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) 64 #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) 68 #define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4)) 72 #define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4)) 76 #define CR_ODEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODEN_BitNumber * 4)) 80 #define CR_ODSWEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODSWEN_BitNumber * 4)) 85 #define CR_MRUDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MRUDS_BitNumber * 4)) 89 #define CR_LPUDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LPUDS_BitNumber * 4)) 95 #define CR_MRLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MRLVDS_BitNumber * 4)) [all …]
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/STM32F4xx_StdPeriph_Driver/src/ |
H A D | stm32f4xx_pwr.c | 58 #define CR_OFFSET (PWR_OFFSET + 0x00) macro 60 #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) 64 #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) 68 #define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4)) 72 #define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4)) 76 #define CR_ODEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODEN_BitNumber * 4)) 80 #define CR_ODSWEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODSWEN_BitNumber * 4)) 85 #define CR_MRUDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MRUDS_BitNumber * 4)) 89 #define CR_LPUDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LPUDS_BitNumber * 4)) 95 #define CR_MRLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MRLVDS_BitNumber * 4)) [all …]
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H A D | stm32f4xx_rcc.c | 76 #define CR_OFFSET (RCC_OFFSET + 0x00) macro 78 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) 81 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) 84 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) 87 #define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4)) 91 #define CR_PLLSAION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/i2c/busses/ |
H A D | i2c-iop3xx.c | 61 __raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_reset() 89 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_enable() 95 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_transaction_cleanup() 100 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_transaction_cleanup() 233 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_send_target_addr() 249 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_send_target_addr() 259 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_write_byte() 271 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_write_byte() 281 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_read_byte() 293 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_read_byte() [all …]
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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/i2c/busses/ |
H A D | i2c-iop3xx.c | 61 __raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_reset() 89 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_enable() 95 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_transaction_cleanup() 100 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_transaction_cleanup() 233 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_send_target_addr() 249 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_send_target_addr() 259 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_write_byte() 271 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_write_byte() 281 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_read_byte() 293 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_read_byte() [all …]
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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/i2c/busses/ |
H A D | i2c-iop3xx.c | 61 __raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_reset() 89 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_enable() 95 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_transaction_cleanup() 100 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_transaction_cleanup() 233 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_send_target_addr() 249 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_send_target_addr() 259 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_write_byte() 271 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_write_byte() 281 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_read_byte() 293 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_read_byte() [all …]
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/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/mips/ar7/ |
H A D | irq.c | 22 #define CR_OFFSET(irq) (REG_OFFSET(irq, 1)) /* 0x10 */ macro 54 REG(CR_OFFSET(d->irq - ar7_irq_base))); in ar7_ack_irq() 95 writel(0xffffffff, REG(CR_OFFSET(0))); in ar7_irq_init() 96 writel(0xff, REG(CR_OFFSET(32))); in ar7_irq_init() 143 writel(1, REG(CR_OFFSET(irq))); in ar7_cascade()
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/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/mips/ar7/ |
H A D | irq.c | 22 #define CR_OFFSET(irq) (REG_OFFSET(irq, 1)) /* 0x10 */ macro 54 REG(CR_OFFSET(d->irq - ar7_irq_base))); in ar7_ack_irq() 95 writel(0xffffffff, REG(CR_OFFSET(0))); in ar7_irq_init() 96 writel(0xff, REG(CR_OFFSET(32))); in ar7_irq_init() 143 writel(1, REG(CR_OFFSET(irq))); in ar7_cascade()
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/dports/multimedia/libv4l/linux-5.13-rc2/arch/mips/ar7/ |
H A D | irq.c | 22 #define CR_OFFSET(irq) (REG_OFFSET(irq, 1)) /* 0x10 */ macro 54 REG(CR_OFFSET(d->irq - ar7_irq_base))); in ar7_ack_irq() 95 writel(0xffffffff, REG(CR_OFFSET(0))); in ar7_irq_init() 96 writel(0xff, REG(CR_OFFSET(32))); in ar7_irq_init() 143 writel(1, REG(CR_OFFSET(irq))); in ar7_cascade()
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/STM32F37x_StdPeriph_Driver/src/ |
H A D | stm32f37x_cec.c | 115 #define CR_OFFSET (CEC_OFFSET + 0x00) macro 117 #define CR_CECEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CECEN_BitNumber * 4)) 121 #define CR_TXSOM_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TXSOM_BitNumber * 4)) 125 #define CR_TXEOM_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TXEOM_BitNumber * 4))
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H A D | stm32f37x_pwr.c | 57 #define CR_OFFSET (PWR_OFFSET + 0x00) macro 59 #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) 63 #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
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H A D | stm32f37x_rcc.c | 77 #define CR_OFFSET (RCC_OFFSET + 0x00) macro 79 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) 83 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) 87 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32F37x_StdPeriph_Driver/src/ |
H A D | stm32f37x_cec.c | 115 #define CR_OFFSET (CEC_OFFSET + 0x00) macro 117 #define CR_CECEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CECEN_BitNumber * 4)) 121 #define CR_TXSOM_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TXSOM_BitNumber * 4)) 125 #define CR_TXEOM_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TXEOM_BitNumber * 4))
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H A D | stm32f37x_pwr.c | 57 #define CR_OFFSET (PWR_OFFSET + 0x00) macro 59 #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) 63 #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
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H A D | stm32f37x_rcc.c | 77 #define CR_OFFSET (RCC_OFFSET + 0x00) macro 79 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) 83 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) 87 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/STM32F10x_StdPeriph_Driver/src/ |
H A D | stm32f10x_pwr.c | 52 #define CR_OFFSET (PWR_OFFSET + 0x00) macro 54 #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) 58 #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
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H A D | stm32f10x_bkp.c | 52 #define CR_OFFSET (BKP_OFFSET + 0x30) macro 54 #define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4)) 58 #define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
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H A D | stm32f10x_rcc.c | 51 #define CR_OFFSET (RCC_OFFSET + 0x00) macro 53 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) 57 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) 62 #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4)) 66 #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4)) 71 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32F10x_StdPeriph_Driver/src/ |
H A D | stm32f10x_pwr.c | 52 #define CR_OFFSET (PWR_OFFSET + 0x00) macro 54 #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) 58 #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
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H A D | stm32f10x_bkp.c | 52 #define CR_OFFSET (BKP_OFFSET + 0x30) macro 54 #define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4)) 58 #define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
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H A D | stm32f10x_rcc.c | 51 #define CR_OFFSET (RCC_OFFSET + 0x00) macro 53 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) 57 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) 62 #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4)) 66 #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4)) 71 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/STM32F30x_StdPeriph_Driver/src/ |
H A D | stm32f30x_pwr.c | 56 #define CR_OFFSET (PWR_OFFSET + 0x00) macro 58 #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) 62 #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
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/dports/games/retroarch/RetroArch-1.9.7/wii/libogc/libogc/ |
H A D | exception_handler.S | 102 stw r3,CR_OFFSET(r4) 154 lwz r4,CR_OFFSET(sp) 194 lwz r4,CR_OFFSET(sp)
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/dports/emulators/mess/mame-mame0226/src/devices/bus/centronics/ |
H A D | epson_lx810l.cpp | 44 #define CR_OFFSET (-14) macro 547 …bitmap.plot_box(m_real_cr_pos + CR_OFFSET - 10 - bordersize, PAPER_HEIGHT - 36 - bordersize, 20 + … in screen_update_lx810l() 548 …bitmap.plot_box(m_real_cr_pos + CR_OFFSET - 10, PAPER_HEIGHT - 36, 20, 36, m_e05a30->ready_led() ?… in screen_update_lx810l() 577 m_bitmap.pix(y, m_real_cr_pos + CR_OFFSET) = 0x000000; in WRITE_LINE_MEMBER()
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/dports/emulators/mame/mame-mame0226/src/devices/bus/centronics/ |
H A D | epson_lx810l.cpp | 44 #define CR_OFFSET (-14) macro 547 …bitmap.plot_box(m_real_cr_pos + CR_OFFSET - 10 - bordersize, PAPER_HEIGHT - 36 - bordersize, 20 + … in screen_update_lx810l() 548 …bitmap.plot_box(m_real_cr_pos + CR_OFFSET - 10, PAPER_HEIGHT - 36, 20, 36, m_e05a30->ready_led() ?… in screen_update_lx810l() 577 m_bitmap.pix(y, m_real_cr_pos + CR_OFFSET) = 0x000000; in WRITE_LINE_MEMBER()
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