1 /** 2 ****************************************************************************** 3 * @file stm32f10x_pwr.c 4 * @author MCD Application Team 5 * @version V3.1.2 6 * @date 09/28/2009 7 * @brief This file provides all the PWR firmware functions. 8 ****************************************************************************** 9 * @copy 10 * 11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 * 18 * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2> 19 */ 20 21 /* Includes ------------------------------------------------------------------*/ 22 #include "stm32f10x_pwr.h" 23 #include "stm32f10x_rcc.h" 24 25 /** @addtogroup STM32F10x_StdPeriph_Driver 26 * @{ 27 */ 28 29 /** @defgroup PWR 30 * @brief PWR driver modules 31 * @{ 32 */ 33 34 /** @defgroup PWR_Private_TypesDefinitions 35 * @{ 36 */ 37 38 /** 39 * @} 40 */ 41 42 /** @defgroup PWR_Private_Defines 43 * @{ 44 */ 45 46 /* --------- PWR registers bit address in the alias region ---------- */ 47 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE) 48 49 /* --- CR Register ---*/ 50 51 /* Alias word address of DBP bit */ 52 #define CR_OFFSET (PWR_OFFSET + 0x00) 53 #define DBP_BitNumber 0x08 54 #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) 55 56 /* Alias word address of PVDE bit */ 57 #define PVDE_BitNumber 0x04 58 #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) 59 60 /* --- CSR Register ---*/ 61 62 /* Alias word address of EWUP bit */ 63 #define CSR_OFFSET (PWR_OFFSET + 0x04) 64 #define EWUP_BitNumber 0x08 65 #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) 66 67 /* ------------------ PWR registers bit mask ------------------------ */ 68 69 /* CR register bit mask */ 70 #define CR_PDDS_Set ((uint32_t)0x00000002) 71 #define CR_DS_Mask ((uint32_t)0xFFFFFFFC) 72 #define CR_CWUF_Set ((uint32_t)0x00000004) 73 #define CR_PLS_Mask ((uint32_t)0xFFFFFF1F) 74 75 /* --------- Cortex System Control register bit mask ---------------- */ 76 77 /* Cortex System Control register address */ 78 #define SCB_SysCtrl ((uint32_t)0xE000ED10) 79 80 /* SLEEPDEEP bit mask */ 81 #define SysCtrl_SLEEPDEEP_Set ((uint32_t)0x00000004) 82 /** 83 * @} 84 */ 85 86 /** @defgroup PWR_Private_Macros 87 * @{ 88 */ 89 90 /** 91 * @} 92 */ 93 94 /** @defgroup PWR_Private_Variables 95 * @{ 96 */ 97 98 /** 99 * @} 100 */ 101 102 /** @defgroup PWR_Private_FunctionPrototypes 103 * @{ 104 */ 105 106 /** 107 * @} 108 */ 109 110 /** @defgroup PWR_Private_Functions 111 * @{ 112 */ 113 114 /** 115 * @brief Deinitializes the PWR peripheral registers to their default reset values. 116 * @param None 117 * @retval None 118 */ PWR_DeInit(void)119void PWR_DeInit(void) 120 { 121 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); 122 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); 123 } 124 125 /** 126 * @brief Enables or disables access to the RTC and backup registers. 127 * @param NewState: new state of the access to the RTC and backup registers. 128 * This parameter can be: ENABLE or DISABLE. 129 * @retval None 130 */ PWR_BackupAccessCmd(FunctionalState NewState)131void PWR_BackupAccessCmd(FunctionalState NewState) 132 { 133 /* Check the parameters */ 134 assert_param(IS_FUNCTIONAL_STATE(NewState)); 135 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; 136 } 137 138 /** 139 * @brief Enables or disables the Power Voltage Detector(PVD). 140 * @param NewState: new state of the PVD. 141 * This parameter can be: ENABLE or DISABLE. 142 * @retval None 143 */ PWR_PVDCmd(FunctionalState NewState)144void PWR_PVDCmd(FunctionalState NewState) 145 { 146 /* Check the parameters */ 147 assert_param(IS_FUNCTIONAL_STATE(NewState)); 148 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; 149 } 150 151 /** 152 * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). 153 * @param PWR_PVDLevel: specifies the PVD detection level 154 * This parameter can be one of the following values: 155 * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V 156 * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V 157 * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V 158 * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V 159 * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V 160 * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V 161 * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V 162 * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V 163 * @retval None 164 */ PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)165void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) 166 { 167 uint32_t tmpreg = 0; 168 /* Check the parameters */ 169 assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); 170 tmpreg = PWR->CR; 171 /* Clear PLS[7:5] bits */ 172 tmpreg &= CR_PLS_Mask; 173 /* Set PLS[7:5] bits according to PWR_PVDLevel value */ 174 tmpreg |= PWR_PVDLevel; 175 /* Store the new value */ 176 PWR->CR = tmpreg; 177 } 178 179 /** 180 * @brief Enables or disables the WakeUp Pin functionality. 181 * @param NewState: new state of the WakeUp Pin functionality. 182 * This parameter can be: ENABLE or DISABLE. 183 * @retval None 184 */ PWR_WakeUpPinCmd(FunctionalState NewState)185void PWR_WakeUpPinCmd(FunctionalState NewState) 186 { 187 /* Check the parameters */ 188 assert_param(IS_FUNCTIONAL_STATE(NewState)); 189 *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; 190 } 191 192 /** 193 * @brief Enters STOP mode. 194 * @param PWR_Regulator: specifies the regulator state in STOP mode. 195 * This parameter can be one of the following values: 196 * @arg PWR_Regulator_ON: STOP mode with regulator ON 197 * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode 198 * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. 199 * This parameter can be one of the following values: 200 * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction 201 * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction 202 * @retval None 203 */ PWR_EnterSTOPMode(uint32_t PWR_Regulator,uint8_t PWR_STOPEntry)204void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) 205 { 206 uint32_t tmpreg = 0; 207 /* Check the parameters */ 208 assert_param(IS_PWR_REGULATOR(PWR_Regulator)); 209 assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); 210 211 /* Select the regulator state in STOP mode ---------------------------------*/ 212 tmpreg = PWR->CR; 213 /* Clear PDDS and LPDS bits */ 214 tmpreg &= CR_DS_Mask; 215 /* Set LPDS bit according to PWR_Regulator value */ 216 tmpreg |= PWR_Regulator; 217 /* Store the new value */ 218 PWR->CR = tmpreg; 219 /* Set SLEEPDEEP bit of Cortex System Control Register */ 220 *(__IO uint32_t *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set; 221 222 /* Select STOP mode entry --------------------------------------------------*/ 223 if(PWR_STOPEntry == PWR_STOPEntry_WFI) 224 { 225 /* Request Wait For Interrupt */ 226 __WFI(); 227 } 228 else 229 { 230 /* Request Wait For Event */ 231 __WFE(); 232 } 233 } 234 235 /** 236 * @brief Enters STANDBY mode. 237 * @param None 238 * @retval None 239 */ PWR_EnterSTANDBYMode(void)240void PWR_EnterSTANDBYMode(void) 241 { 242 /* Clear Wake-up flag */ 243 PWR->CR |= CR_CWUF_Set; 244 /* Select STANDBY mode */ 245 PWR->CR |= CR_PDDS_Set; 246 /* Set SLEEPDEEP bit of Cortex System Control Register */ 247 *(__IO uint32_t *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set; 248 /* This option is used to ensure that store operations are completed */ 249 #if defined ( __CC_ARM ) 250 __force_stores(); 251 #endif 252 /* Request Wait For Interrupt */ 253 __WFI(); 254 } 255 256 /** 257 * @brief Checks whether the specified PWR flag is set or not. 258 * @param PWR_FLAG: specifies the flag to check. 259 * This parameter can be one of the following values: 260 * @arg PWR_FLAG_WU: Wake Up flag 261 * @arg PWR_FLAG_SB: StandBy flag 262 * @arg PWR_FLAG_PVDO: PVD Output 263 * @retval The new state of PWR_FLAG (SET or RESET). 264 */ PWR_GetFlagStatus(uint32_t PWR_FLAG)265FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) 266 { 267 FlagStatus bitstatus = RESET; 268 /* Check the parameters */ 269 assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); 270 271 if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) 272 { 273 bitstatus = SET; 274 } 275 else 276 { 277 bitstatus = RESET; 278 } 279 /* Return the flag status */ 280 return bitstatus; 281 } 282 283 /** 284 * @brief Clears the PWR's pending flags. 285 * @param PWR_FLAG: specifies the flag to clear. 286 * This parameter can be one of the following values: 287 * @arg PWR_FLAG_WU: Wake Up flag 288 * @arg PWR_FLAG_SB: StandBy flag 289 * @retval None 290 */ PWR_ClearFlag(uint32_t PWR_FLAG)291void PWR_ClearFlag(uint32_t PWR_FLAG) 292 { 293 /* Check the parameters */ 294 assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); 295 296 PWR->CR |= PWR_FLAG << 2; 297 } 298 299 /** 300 * @} 301 */ 302 303 /** 304 * @} 305 */ 306 307 /** 308 * @} 309 */ 310 311 /******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ 312