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Searched refs:FCR0_PRID (Results 1 – 22 of 22) sorted by relevance

/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/target-mips/
H A Dtranslate_init.c343 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
379 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
423 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
462 (0x93 << FCR0_PRID),
492 (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
520 (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
583 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
618 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
693 (1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) |
729 (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
[all …]
H A Dcpu.h112 #define FCR0_PRID 8 in run_dbwrap_watch1()
/dports/emulators/unicorn/unicorn-1.0.2/qemu/target-mips/
H A Dtranslate_init.c343 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
379 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
423 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
462 (0x93 << FCR0_PRID),
492 (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
520 (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
583 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
618 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
693 (1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) |
729 (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
[all …]
H A Dcpu.h112 #define FCR0_PRID 8 macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/mips/
H A Dtranslate_init.inc.c244 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
276 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
318 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
405 (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID),
506 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
526 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
573 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
602 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
678 (0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
776 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
[all …]
H A Dcpu.h60 #define FCR0_PRID 8 macro
/dports/emulators/qemu42/qemu-4.2.1/target/mips/
H A Dtranslate_init.inc.c244 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
276 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
318 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
405 (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID),
506 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
526 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
573 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
602 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
678 (0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
776 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
[all …]
H A Dcpu.h60 #define FCR0_PRID 8 macro
/dports/emulators/qemu-utils/qemu-4.2.1/target/mips/
H A Dtranslate_init.inc.c244 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
276 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
318 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
405 (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID),
506 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
526 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
573 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
602 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
678 (0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
776 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
[all …]
H A Dcpu.h60 #define FCR0_PRID 8 macro
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/mips/
H A Dtranslate_init.inc.c244 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
276 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
318 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
542 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
570 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
643 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
687 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
719 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
795 (0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
893 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
[all …]
H A Dcpu.h65 #define FCR0_PRID 8 macro
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/mips/
H A Dtranslate_init.inc.c244 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
276 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
318 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
405 (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID),
505 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
525 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
572 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
601 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
677 (0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
735 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
[all …]
H A Dcpu.h64 #define FCR0_PRID 8 macro
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/mips/
H A Dcpu-defs.c.inc244 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
276 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
318 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
406 (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID),
508 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
529 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
576 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
605 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
681 (0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
779 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
[all …]
H A Dcpu.h61 #define FCR0_PRID 8
/dports/emulators/qemu/qemu-6.2.0/target/mips/
H A Dcpu-defs.c.inc244 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
276 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
318 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
405 (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID),
507 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
528 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
575 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
604 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
680 (0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
778 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
[all …]
H A Dcpu.h61 #define FCR0_PRID 8 macro
/dports/emulators/qemu60/qemu-6.0.0/target/mips/
H A Dcpu-defs.c.inc244 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
276 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
318 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
406 (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID),
508 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
529 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
576 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
605 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
681 (0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
779 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
[all …]
H A Dcpu.h61 #define FCR0_PRID 8 macro
/dports/emulators/qemu5/qemu-5.2.0/target/mips/
H A Dtranslate_init.c.inc244 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
276 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
318 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
406 (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID),
507 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
527 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
574 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
603 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
679 (0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
777 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
[all …]
H A Dcpu.h61 #define FCR0_PRID 8 macro