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Searched refs:FPSCR_SET (Results 1 – 12 of 12) sorted by relevance

/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/ppc/
H A Didecode_expression.h344 #define FPSCR_SET(REG, VAL) MBLIT32(FPSCR, REG*4, REG*4+3, VAL) macro
H A Dppc-instructions4647 FPSCR_SET(BFA, 0); /* FPSCR_END fixes up FEX/VX */
4652 FPSCR_SET(BF, U);
H A DChangeLog2373 * idecode_expression.h (FPSCR_SET): New macro, set specific FPSCR
/dports/devel/avr-gdb/gdb-7.3.1/sim/ppc/
H A Didecode_expression.h344 #define FPSCR_SET(REG, VAL) MBLIT32(FPSCR, REG*4, REG*4+3, VAL) macro
H A Dppc-instructions4683 FPSCR_SET(BFA, 0); /* FPSCR_END fixes up FEX/VX */
4688 FPSCR_SET(BF, U);
H A DChangeLog2708 * idecode_expression.h (FPSCR_SET): New macro, set specific FPSCR
/dports/devel/gdb761/gdb-7.6.1/sim/ppc/
H A Didecode_expression.h343 #define FPSCR_SET(REG, VAL) MBLIT32(FPSCR, REG*4, REG*4+3, VAL) macro
H A Dppc-instructions4682 FPSCR_SET(BFA, 0); /* FPSCR_END fixes up FEX/VX */
4687 FPSCR_SET(BF, U);
H A DChangeLog2769 * idecode_expression.h (FPSCR_SET): New macro, set specific FPSCR
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/ppc/
H A Didecode_expression.h344 #define FPSCR_SET(REG, VAL) MBLIT32(FPSCR, REG*4, REG*4+3, VAL) macro
H A Dppc-instructions4647 FPSCR_SET(BFA, 0); /* FPSCR_END fixes up FEX/VX */
4652 FPSCR_SET(BF, U);
H A DChangeLog2373 * idecode_expression.h (FPSCR_SET): New macro, set specific FPSCR