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Searched refs:reg_proc (Results 1 – 25 of 112) sorted by relevance

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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/mailbox/
H A Dstm32-ipcc.c51 void __iomem *reg_proc; member
92 mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR); in stm32_ipcc_rx_irq()
121 tosr = readl_relaxed(ipcc->reg_proc + IPCC_XTOYSR); in stm32_ipcc_tx_irq()
122 mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR); in stm32_ipcc_tx_irq()
158 stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR, in stm32_ipcc_send_data()
178 stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR, in stm32_ipcc_startup()
191 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR, in stm32_ipcc_shutdown()
352 ipcc->xmr = readl_relaxed(ipcc->reg_proc + IPCC_XMR); in stm32_ipcc_suspend()
353 ipcc->xcr = readl_relaxed(ipcc->reg_proc + IPCC_XCR); in stm32_ipcc_suspend()
362 writel_relaxed(ipcc->xmr, ipcc->reg_proc + IPCC_XMR); in stm32_ipcc_resume()
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/mailbox/
H A Dstm32-ipcc.c51 void __iomem *reg_proc; member
92 mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR); in stm32_ipcc_rx_irq()
121 tosr = readl_relaxed(ipcc->reg_proc + IPCC_XTOYSR); in stm32_ipcc_tx_irq()
122 mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR); in stm32_ipcc_tx_irq()
158 stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR, in stm32_ipcc_send_data()
178 stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR, in stm32_ipcc_startup()
191 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR, in stm32_ipcc_shutdown()
352 ipcc->xmr = readl_relaxed(ipcc->reg_proc + IPCC_XMR); in stm32_ipcc_suspend()
353 ipcc->xcr = readl_relaxed(ipcc->reg_proc + IPCC_XCR); in stm32_ipcc_suspend()
362 writel_relaxed(ipcc->xmr, ipcc->reg_proc + IPCC_XMR); in stm32_ipcc_resume()
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/mailbox/
H A Dstm32-ipcc.c51 void __iomem *reg_proc; member
92 mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR); in stm32_ipcc_rx_irq()
121 tosr = readl_relaxed(ipcc->reg_proc + IPCC_XTOYSR); in stm32_ipcc_tx_irq()
122 mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR); in stm32_ipcc_tx_irq()
158 stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR, in stm32_ipcc_send_data()
178 stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR, in stm32_ipcc_startup()
191 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR, in stm32_ipcc_shutdown()
352 ipcc->xmr = readl_relaxed(ipcc->reg_proc + IPCC_XMR); in stm32_ipcc_suspend()
353 ipcc->xcr = readl_relaxed(ipcc->reg_proc + IPCC_XCR); in stm32_ipcc_suspend()
362 writel_relaxed(ipcc->xmr, ipcc->reg_proc + IPCC_XMR); in stm32_ipcc_resume()
[all …]
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/mailbox/
H A Dstm32-ipcc.c40 void __iomem *reg_proc; member
73 if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id)) in stm32_ipcc_send()
77 setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id)); in stm32_ipcc_send()
92 val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_recv()
97 setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id)); in stm32_ipcc_recv()
129 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; in stm32_ipcc_probe()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/mailbox/
H A Dstm32-ipcc.c40 void __iomem *reg_proc; member
73 if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id)) in stm32_ipcc_send()
77 setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id)); in stm32_ipcc_send()
92 val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_recv()
97 setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id)); in stm32_ipcc_recv()
129 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; in stm32_ipcc_probe()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/mailbox/
H A Dstm32-ipcc.c40 void __iomem *reg_proc; member
73 if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id)) in stm32_ipcc_send()
77 setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id)); in stm32_ipcc_send()
92 val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_recv()
97 setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id)); in stm32_ipcc_recv()
129 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; in stm32_ipcc_probe()
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/mailbox/
H A Dstm32-ipcc.c40 void __iomem *reg_proc; member
73 if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id)) in stm32_ipcc_send()
77 setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id)); in stm32_ipcc_send()
92 val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_recv()
97 setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id)); in stm32_ipcc_recv()
129 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; in stm32_ipcc_probe()
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/mailbox/
H A Dstm32-ipcc.c40 void __iomem *reg_proc; member
73 if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id)) in stm32_ipcc_send()
77 setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id)); in stm32_ipcc_send()
92 val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_recv()
97 setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id)); in stm32_ipcc_recv()
129 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; in stm32_ipcc_probe()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/mailbox/
H A Dstm32-ipcc.c40 void __iomem *reg_proc; member
73 if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id)) in stm32_ipcc_send()
77 setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id)); in stm32_ipcc_send()
92 val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_recv()
97 setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id)); in stm32_ipcc_recv()
129 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; in stm32_ipcc_probe()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/mailbox/
H A Dstm32-ipcc.c40 void __iomem *reg_proc; member
73 if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id)) in stm32_ipcc_send()
77 setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id)); in stm32_ipcc_send()
92 val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_recv()
97 setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id)); in stm32_ipcc_recv()
129 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; in stm32_ipcc_probe()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/mailbox/
H A Dstm32-ipcc.c40 void __iomem *reg_proc; member
73 if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id)) in stm32_ipcc_send()
77 setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id)); in stm32_ipcc_send()
92 val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_recv()
97 setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id)); in stm32_ipcc_recv()
129 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; in stm32_ipcc_probe()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/mailbox/
H A Dstm32-ipcc.c40 void __iomem *reg_proc; member
73 if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id)) in stm32_ipcc_send()
77 setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id)); in stm32_ipcc_send()
92 val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_recv()
97 setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id)); in stm32_ipcc_recv()
129 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; in stm32_ipcc_probe()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/mailbox/
H A Dstm32-ipcc.c40 void __iomem *reg_proc; member
73 if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id)) in stm32_ipcc_send()
77 setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id)); in stm32_ipcc_send()
92 val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_recv()
97 setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id)); in stm32_ipcc_recv()
129 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; in stm32_ipcc_probe()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/mailbox/
H A Dstm32-ipcc.c40 void __iomem *reg_proc; member
73 if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id)) in stm32_ipcc_send()
77 setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id)); in stm32_ipcc_send()
92 val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_recv()
97 setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id)); in stm32_ipcc_recv()
129 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; in stm32_ipcc_probe()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/mailbox/
H A Dstm32-ipcc.c40 void __iomem *reg_proc; member
73 if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id)) in stm32_ipcc_send()
77 setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id)); in stm32_ipcc_send()
92 val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_recv()
97 setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id)); in stm32_ipcc_recv()
129 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; in stm32_ipcc_probe()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/mailbox/
H A Dstm32-ipcc.c40 void __iomem *reg_proc; member
73 if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id)) in stm32_ipcc_send()
77 setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id)); in stm32_ipcc_send()
92 val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_recv()
97 setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id)); in stm32_ipcc_recv()
129 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; in stm32_ipcc_probe()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/mailbox/
H A Dstm32-ipcc.c40 void __iomem *reg_proc; member
73 if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id)) in stm32_ipcc_send()
77 setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id)); in stm32_ipcc_send()
92 val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_recv()
97 setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id)); in stm32_ipcc_recv()
129 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; in stm32_ipcc_probe()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/mailbox/
H A Dstm32-ipcc.c40 void __iomem *reg_proc; member
73 if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id)) in stm32_ipcc_send()
77 setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id)); in stm32_ipcc_send()
92 val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_recv()
97 setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id)); in stm32_ipcc_recv()
129 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; in stm32_ipcc_probe()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/mailbox/
H A Dstm32-ipcc.c40 void __iomem *reg_proc; member
73 if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id)) in stm32_ipcc_send()
77 setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id)); in stm32_ipcc_send()
92 val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_recv()
97 setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id)); in stm32_ipcc_recv()
129 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; in stm32_ipcc_probe()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/mailbox/
H A Dstm32-ipcc.c40 void __iomem *reg_proc; member
73 if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id)) in stm32_ipcc_send()
77 setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id)); in stm32_ipcc_send()
92 val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_recv()
97 setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id)); in stm32_ipcc_recv()
129 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; in stm32_ipcc_probe()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/mailbox/
H A Dstm32-ipcc.c40 void __iomem *reg_proc; member
73 if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id)) in stm32_ipcc_send()
77 setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id)); in stm32_ipcc_send()
92 val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_recv()
97 setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id)); in stm32_ipcc_recv()
129 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; in stm32_ipcc_probe()
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/mailbox/
H A Dstm32-ipcc.c40 void __iomem *reg_proc; member
73 if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id)) in stm32_ipcc_send()
77 setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id)); in stm32_ipcc_send()
92 val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_recv()
97 setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id)); in stm32_ipcc_recv()
129 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; in stm32_ipcc_probe()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/mailbox/
H A Dstm32-ipcc.c40 void __iomem *reg_proc; member
73 if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id)) in stm32_ipcc_send()
77 setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id)); in stm32_ipcc_send()
92 val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_recv()
97 setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id)); in stm32_ipcc_recv()
129 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; in stm32_ipcc_probe()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/mailbox/
H A Dstm32-ipcc.c40 void __iomem *reg_proc; member
73 if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id)) in stm32_ipcc_send()
77 setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id)); in stm32_ipcc_send()
92 val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_recv()
97 setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id)); in stm32_ipcc_recv()
129 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; in stm32_ipcc_probe()
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/mailbox/
H A Dstm32-ipcc.c40 void __iomem *reg_proc; member
73 if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id)) in stm32_ipcc_send()
77 setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id)); in stm32_ipcc_send()
92 val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_recv()
97 setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id)); in stm32_ipcc_recv()
129 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; in stm32_ipcc_probe()

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