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/freebsd/crypto/openssl/crypto/bn/asm/
H A Dppc.pl118 $ST= "stw"; # store
142 $ST= "std"; # store
1812 $ST r9,`0*$BNSZ`(r3)
1826 $ST r9,`2*$BNSZ`(r3)
1849 $ST r9,`0*$BNSZ`(r3)
1863 $ST r9,`1*$BNSZ`(r3)
1876 $ST r9,`2*$BNSZ`(r3)
1926 $ST r9,`0*$BNSZ`(r3)
1979 $ST r9,0(r3)
1991 $ST r9,0(r3)
[all …]
H A Dppc-mont.pl58 $ST= "stw"; # store
67 $PUSH= $ST;
79 $ST= "std"; # store
88 $PUSH= $ST;
232 $ST $hi1,$BNSZ($tp)
298 $ST $hi1,$BNSZ($tp)
767 $ST $a1,$SIZE_T*2($tp)
768 $ST $a2,$SIZE_T*3($tp)
769 $ST $a3,$SIZE_T*4($tp)
815 $ST $t0,$SIZE_T*1($bp)
[all …]
H A Dmips.pl64 $ST="sd";
79 $ST="sw";
188 $ST $t1,0($a0)
248 $ST $t1,0($a0)
340 $ST $v0,0($a0)
384 $ST $v0,0($a0)
465 $ST $t1,0($a0)
504 $ST $t1,0($a0)
631 $ST $t0,0($a0)
763 $ST $t0,0($a0)
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsLegalizerInfo.cpp83 .legalIf([=, &ST](const LegalityQuery &Query) { in MipsLegalizerInfo()
107 .legalIf([=, &ST](const LegalityQuery &Query) { in MipsLegalizerInfo()
115 if (ST.hasMSA() && CheckTy0Ty1MemSizeAlign( in MipsLegalizerInfo()
126 .customIf([=, &ST](const LegalityQuery &Query) { in MipsLegalizerInfo()
141 if (!ST.systemSupportsUnalignedAccess() && in MipsLegalizerInfo()
199 .legalIf([=, &ST](const LegalityQuery &Query) { in MipsLegalizerInfo()
242 .legalIf([=, &ST](const LegalityQuery &Query) { in MipsLegalizerInfo()
247 .lowerIf([=, &ST](const LegalityQuery &Query) { in MipsLegalizerInfo()
330 verify(*ST.getInstrInfo()); in MipsLegalizerInfo()
478 *ST.getRegBankInfo())) in SelectMSA3OpIntrinsic()
[all …]
/freebsd/contrib/file/magic/Magdir/
H A Duf229 >>28 lelong 0x00ff6919 ST STM32L4xx
30 >>28 lelong 0x04240bdf ST STM32L5xx
35 >>28 lelong 0x1e1f432d ST STM32L1xx
36 >>28 lelong 0x202e3a91 ST STM32L0xx
37 >>28 lelong 0x21460ff0 ST STM32WLxx
39 >>28 lelong 0x300f5633 ST STM32G0xx
41 >>28 lelong 0x4c71240a ST STM32G4xx
43 >>28 lelong 0x53b80f00 ST STM32F7xx
45 >>28 lelong 0x57755a57 ST STM32F401
47 >>28 lelong 0x5d1a0a2e ST STM32F2xx
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVLegalizerInfo.cpp103 if (ST.is64Bit()) in RISCVLegalizerInfo()
111 if (ST.is64Bit()) { in RISCVLegalizerInfo()
144 if (ST.hasStdExtZbb() || ST.hasStdExtZbkb()) { in RISCVLegalizerInfo()
147 if (ST.is64Bit()) in RISCVLegalizerInfo()
156 if (ST.hasStdExtZbb() || ST.hasStdExtZbkb()) in RISCVLegalizerInfo()
164 if (ST.hasStdExtZbb()) { in RISCVLegalizerInfo()
250 if (ST.hasStdExtM() || ST.hasStdExtZmmul()) { in RISCVLegalizerInfo()
281 if (ST.hasStdExtM()) { in RISCVLegalizerInfo()
295 if (ST.hasStdExtZbb()) in RISCVLegalizerInfo()
301 if (ST.hasStdExtZbb()) in RISCVLegalizerInfo()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNHazardRecognizer.cpp58 TII(*ST.getInstrInfo()), in GCNHazardRecognizer()
63 TSchedModel.init(&ST); in GCNHazardRecognizer()
131 if (!ST.hasGFX940Insts()) in isXDL()
338 if (ST.hasNSAtoVMEMBug()) in PreEmitNoopsCommon()
622 if (!ST.isXNACKEnabled()) in checkSoftClauseHazards()
1069 if (!ST.hasRFEHazards()) in checkRFEHazards()
1097 if (ST.hasLdsDirect()) { in fixHazards()
2273 if (ST.hasGFX940Insts() && isXDL(ST, *MI) && !isXDL(ST, *MI1)) in checkMAIHazards90A()
2371 if (!ST.hasMAIInsts() || ST.hasGFX90AInsts()) in checkMAILdStHazards()
2520 if (IsMem && ST.hasGFX90AInsts() && !ST.hasGFX940Insts()) { in checkMAIVALUHazards()
[all …]
H A DSIProgramInfo.cpp24 uint64_t SIProgramInfo::getComputePGMRSrc1(const GCNSubtarget &ST) const { in getComputePGMRSrc1()
30 if (ST.hasDX10ClampMode()) in getComputePGMRSrc1()
33 if (ST.hasIEEEMode()) in getComputePGMRSrc1()
36 if (ST.hasRrWGMode()) in getComputePGMRSrc1()
43 const GCNSubtarget &ST) const { in getPGMRSrc1()
45 return getComputePGMRSrc1(ST); in getPGMRSrc1()
51 if (ST.hasDX10ClampMode()) in getPGMRSrc1()
54 if (ST.hasIEEEMode()) in getPGMRSrc1()
57 if (ST.hasRrWGMode()) in getPGMRSrc1()
H A DGCNIterativeScheduler.cpp92 const auto &ST = MF.getSubtarget<GCNSubtarget>(); in printRegions() local
97 OS << "Max RP: " << print(R->MaxPressure, &ST); in printRegions()
115 const auto &ST = MF.getSubtarget<GCNSubtarget>(); in printSchedRP() local
116 OS << "RP before: " << print(Before, &ST) in printSchedRP()
117 << "RP after: " << print(After, &ST); in printSchedRP()
398 const auto &ST = MF.getSubtarget<GCNSubtarget>(); in scheduleRegion() local
404 << print(SchedMaxRP, &ST) in scheduleRegion()
412 const auto &ST = MF.getSubtarget<GCNSubtarget>(); in sortRegionsByPressure() local
436 if (R->MaxPressure.getOccupancy(ST) >= NewOcc) in tryMaximizeOccupancy()
498 if (RP.getOccupancy(ST) < TgtOcc) { in scheduleLegacyMaxOccupancy()
[all …]
H A DSIFrameLowering.cpp228 const GCNSubtarget &ST; member in llvm::PrologEpilogSGPRSpillBuilder
403 if (ST.isAmdPalOS()) { in emitEntryFunctionFlatScratchInit()
555 if (ST.hasSGPRInitBug() || in getEntryFunctionReservedScratchRsrcReg()
591 return ST.enableFlatScratch() ? 1 : ST.getWavefrontSize(); in getScratchScaleFactor()
629 if (!ST.enableFlatScratch()) in emitEntryFunctionPrologue()
644 if (ST.isAmdHsaOrMesa(F)) { in emitEntryFunctionPrologue()
734 if (ST.isAmdPalOS()) { in emitEntryFunctionScratchRsrcRegSetup()
768 if (ST.isWave32()) { in emitEntryFunctionScratchRsrcRegSetup()
1454 if (ST.hasMAIInsts() && !ST.hasGFX90AInsts()) { in processFunctionBeforeFrameIndicesReplaced()
1620 if (!ST.hasGFX90AInsts()) in determineCalleeSaves()
[all …]
H A DAMDGPURemoveIncompatibleFunctions.cpp83 const SubtargetSubTypeKV *getGPUInfo(const GCNSubtarget &ST, in getGPUInfo() argument
85 for (const SubtargetSubTypeKV &KV : ST.getAllProcessorDescriptions()) in getGPUInfo()
139 const GCNSubtarget *ST = in checkFunction() local
144 StringRef GPUName = ST->getCPU(); in checkFunction()
150 const SubtargetSubTypeKV *GPUInfo = getGPUInfo(*ST, GPUName); in checkFunction()
168 if (ST->hasFeature(Feature) && !GPUFeatureBits.test(Feature)) { in checkFunction()
178 if (ST->getGeneration() < AMDGPUSubtarget::GFX10 && in checkFunction()
179 ST->hasFeature(AMDGPU::FeatureWavefrontSize32)) { in checkFunction()
H A DAMDGPULowerKernelArguments.cpp31 const GCNSubtarget &ST; member in __anon62a4afd90111::PreloadKernelArgInfo
37 PreloadKernelArgInfo(Function &F, const GCNSubtarget &ST) : F(F), ST(ST) { in PreloadKernelArgInfo() argument
44 const unsigned MaxUserSGPRs = ST.getMaxNumUserSGPRs(); in setInitialFreeUserSGPRsCount()
45 GCNUserSGPRUsageInfo UserSGPRInfo(F, ST); in setInitialFreeUserSGPRsCount()
105 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in lowerKernelArguments() local
112 const uint64_t BaseOffset = ST.getExplicitKernelArgOffset(); in lowerKernelArguments()
116 const uint64_t TotalKernArgSize = ST.getKernArgSegmentSize(F, MaxAlign); in lowerKernelArguments()
131 PreloadKernelArgInfo PreloadInfo(F, ST); in lowerKernelArguments()
147 if (Arg.hasInRegAttr() && InPreloadSequence && ST.hasKernargPreload() && in lowerKernelArguments()
148 !ST.needsKernargPreloadBackwardsCompatibility() && in lowerKernelArguments()
[all …]
H A DSIMachineFunctionInfo.cpp48 WavesPerEU = ST.getWavesPerEU(F); in SIMachineFunctionInfo()
65 MayNeedAGPRs = ST.hasMAIInsts(); in SIMachineFunctionInfo()
88 if (!ST.enableFlatScratch()) { in SIMachineFunctionInfo()
104 if (ST.hasGFX90AInsts() && in SIMachineFunctionInfo()
127 ST.getMaxWorkitemID(F, 1) != 0) in SIMachineFunctionInfo()
131 ST.getMaxWorkitemID(F, 2) != 0) in SIMachineFunctionInfo()
144 if (!ST.flatScratchIsArchitected()) { in SIMachineFunctionInfo()
168 if (ST.hasMAIInsts() && !ST.hasGFX90AInsts()) { in SIMachineFunctionInfo()
406 unsigned WaveSize = ST.getWavefrontSize(); in allocateSGPRSpillToVGPRLane()
588 if (!ST.isAmdPalOS()) in getGITPtrLoReg()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.h35 const RISCVSubtarget *ST; variable
38 const RISCVSubtarget *getST() const { return ST; } in getST()
61 TLI(ST->getTargetLowering()) {} in RISCVTTIImpl()
123 return ST->useRVVForFixedLengthVectors() ? 16 : 0; in getMinVectorRegisterBitWidth()
195 if (!ST->hasVInstructions()) in isLegalMaskedLoadStore()
220 if (!ST->hasVInstructions()) in isLegalMaskedGatherScatter()
245 return ST->is64Bit() && !ST->hasVInstructionsI64(); in forceScalarizeMaskedGather()
250 return ST->is64Bit() && !ST->hasVInstructionsI64(); in forceScalarizeMaskedScatter()
262 if (!ST->hasVInstructions() || in getVPLegalizationStrategy()
320 if (ST->hasStdExtF()) in getNumberOfRegisters()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVModuleAnalysis.cpp160 if (ST->isOpenCLEnv()) { in setBaseInfo()
405 const SPIRVSubtarget &ST) { in getAndAddRequirements() argument
539 if (ST.isOpenCLEnv()) { in initAvailableCapabilities()
544 if (ST.isVulkanEnv()) { in initAvailableCapabilities()
553 const SPIRVSubtarget &ST) { in initAvailableCapabilitiesForOpenCL() argument
569 if (ST.isAtLeastSPIRVVer(11) && ST.isAtLeastOpenCLVer(22)) in initAvailableCapabilitiesForOpenCL()
571 if (ST.isAtLeastSPIRVVer(13)) in initAvailableCapabilitiesForOpenCL()
579 if (ST.isAtLeastSPIRVVer(14)) in initAvailableCapabilitiesForOpenCL()
740 if (!ST.isOpenCLEnv()) in addInstrRequirements()
1057 ST = TM.getSubtargetImpl(); in runOnModule()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCTargetTransformInfo.h33 const ARCSubtarget *ST; variable
36 const ARCSubtarget *getST() const { return ST; } in getST()
41 : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl()), in ARCTTIImpl()
42 TLI(ST->getTargetLowering()) {} in ARCTTIImpl()
46 : BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {} in ARCTTIImpl()
48 : BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)), in ARCTTIImpl()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.h48 const AArch64Subtarget *ST; variable
75 TLI(ST->getTargetLowering()) {} in AArch64TTIImpl()
114 if (ST->hasNEON()) in getNumberOfRegisters()
140 return ST->getVScaleForTuning(); in getVScaleForTuning()
245 if (Ty->isBFloatTy() && ST->hasBF16()) in isElementTypeLegalForScalableVector()
259 if (!ST->hasSVE()) in isLegalMaskedLoadStore()
279 if (!ST->hasSVE() || !ST->isNeonAvailable()) in isLegalMaskedGatherScatter()
339 if (ST->isLittleEndian()) in isLegalNTLoad()
362 return ST->hasSVE() ? 5 : 0; in getMinTripCountTailFoldingThreshold()
366 if (ST->hasSVE()) in getPreferredTailFoldingStyle()
[all …]
H A DAArch64StackTaggingPreRA.cpp262 SlotWithTag ST{*I}; in findFirstSlotCandidate() local
263 if (isSlotPreAllocated(MFI, ST.FI)) in findFirstSlotCandidate()
290 LLVM_DEBUG(dbgs() << "[" << ST.FI << ":" << ST.Tag << "] use of %" in findFirstSlotCandidate()
297 int TotalScore = RetagScore[ST] += Score; in findFirstSlotCandidate()
301 MaxScoreST = ST; in findFirstSlotCandidate()
315 SlotWithTag ST{*I}; in findFirstSlotCandidate() local
316 if (ST.Tag == 0) { in findFirstSlotCandidate()
317 SwapST = ST; in findFirstSlotCandidate()
326 SlotWithTag ST{*I}; in findFirstSlotCandidate() local
328 if (ST == MaxScoreST) { in findFirstSlotCandidate()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp114 if (ST->isMClass() && ST->isThumb2() && in getPreferredAddressingMode()
307 if (!ST->isThumb()) { in getIntImmCost()
314 if (ST->isThumb2()) { in getIntImmCost()
438 if (Inst && ((ST->hasV6Ops() && !ST->isThumb()) || ST->isThumb2()) && in getIntImmCostInst()
464 (ST->hasNEON() || ST->hasMVEIntegerOps())) { in getCFInstrCost()
1074 if (ST->hasNEON()) { in getAddressComputationCost()
1217 if (ST->hasNEON()) { in getShuffleCost()
1341 if (ST->hasNEON()) { in getArithmeticInstrCost()
1714 ST->hasMVEIntegerOps() ? 128 : (ST->hasNEON() ? 64 : -1); in getArithmeticReductionCost()
2023 return !ST->hasFPARMv8Base() && !ST->hasVFP2Base(); in isLoweredToCall()
[all …]
H A DARMSLSHardening.cpp38 const ARMSubtarget *ST; member in __anona3aa1f7f0111::ARMSLSHardening
70 static void insertSpeculationBarrier(const ARMSubtarget *ST, in insertSpeculationBarrier() argument
82 const TargetInstrInfo *TII = ST->getInstrInfo(); in insertSpeculationBarrier()
83 assert(ST->hasDataBarrier() || ST->hasSB()); in insertSpeculationBarrier()
84 bool ProduceSB = ST->hasSB() && !AlwaysUseISBDSB; in insertSpeculationBarrier()
95 ST = &MF.getSubtarget<ARMSubtarget>(); in runOnMachineFunction()
108 if (!ST->hardenSlsRetBr()) in hardenReturnsAndBRs()
110 assert(!ST->isThumb1Only()); in hardenReturnsAndBRs()
204 if (ST->isThumb() == T.isThumb) in insertThunks()
207 return ST->isThumb() ? ThumbThunk : ArmThunk; in insertThunks()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/DirectX/
H A DCBufferDataLayout.cpp25 StructType *ST; member
43 LegacyStructLayout &getStructLayout(StructType *ST);
73 if (auto *ST = dyn_cast<StructType>(Ty)) { in getTypeAllocSize() local
74 LegacyStructLayout &Layout = getStructLayout(ST); in getTypeAllocSize()
93 LegacyCBufferLayout::getStructLayout(StructType *ST) { in getStructLayout() argument
94 auto it = StructLayouts.find(ST); in getStructLayout()
100 Layout.ST = ST; in getStructLayout()
101 for (Type *EltTy : ST->elements()) { in getStructLayout()
110 StructLayouts[ST] = Layout; in getStructLayout()
111 return StructLayouts[ST]; in getStructLayout()
/freebsd/contrib/llvm-project/llvm/lib/TableGen/
H A DSetTheory.cpp39 void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts, in apply()
47 void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts, in apply()
53 ST.evaluate(*Expr->arg_begin(), Add, Loc); in apply()
63 void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts, in apply()
69 ST.evaluate(Expr->arg_begin()[0], S1, Loc); in apply()
70 ST.evaluate(Expr->arg_begin()[1], S2, Loc); in apply()
82 void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts, in apply()
88 ST.evaluate(Expr->arg_begin()[0], Set, Loc); in apply()
93 apply2(ST, Expr, Set, II->getValue(), Elts, Loc); in apply()
164 ST.evaluate(Expr->getArg(i), Args[i], Loc); in apply()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCSectionXCOFF.h44 XCOFF::SymbolType ST, SectionKind K, MCSymbolXCOFF *QualName, in MCSectionXCOFF() argument
48 CsectProp(XCOFF::CsectProperties(SMC, ST)), QualName(QualName), in MCSectionXCOFF()
52 (ST == XCOFF::XTY_SD || ST == XCOFF::XTY_CM || ST == XCOFF::XTY_ER) && in MCSectionXCOFF()
56 assert((ST == XCOFF::XTY_CM || ST == XCOFF::XTY_ER) && in MCSectionXCOFF()
61 if (ST != XCOFF::XTY_ER) { in MCSectionXCOFF()
/freebsd/crypto/openssl/crypto/rc4/asm/
H A Drc4-parisc.pl74 $ST="stb";
79 $ST="stw";
110 $ST $TX[0],0($ix)
114 $ST $TY,0($iy)
130 $ST $TX[0],0($iy)
132 $ST $TY,0($ix)
262 $ST %r0,`0*$SZ`($key)
263 $ST %r0,`1*$SZ`($key)
267 $ST @XX[0],0($key)
291 $ST @TX[0],0($YY)
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CompressEVEX.cpp185 static bool isRedundantNewDataDest(MachineInstr &MI, const X86Subtarget &ST) { in isRedundantNewDataDest() argument
203 ST.getInstrInfo()->commuteInstruction(MI, false, 1, 2); in isRedundantNewDataDest()
207 static bool CompressEVEXImpl(MachineInstr &MI, const X86Subtarget &ST) { in CompressEVEXImpl() argument
230 if (!IsND || !isRedundantNewDataDest(MI, ST)) in CompressEVEXImpl()
243 if (usesExtendedRegister(MI) || !checkPredicate(I->NewOpc, &ST) || in CompressEVEXImpl()
248 const MCInstrDesc &NewDesc = ST.getInstrInfo()->get(I->NewOpc); in CompressEVEXImpl()
283 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>(); in runOnMachineFunction() local
284 if (!ST.hasAVX512() && !ST.hasEGPR() && !ST.hasNDD()) in runOnMachineFunction()
292 Changed |= CompressEVEXImpl(MI, ST); in runOnMachineFunction()

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