1 //===-- SIProgramInfo.cpp ----------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 ///
11 /// The SIProgramInfo tracks resource usage and hardware flags for kernels and
12 /// entry functions.
13 //
14 //===----------------------------------------------------------------------===//
15 //
16 
17 #include "SIProgramInfo.h"
18 #include "GCNSubtarget.h"
19 #include "SIDefines.h"
20 #include "Utils/AMDGPUBaseInfo.h"
21 
22 using namespace llvm;
23 
getComputePGMRSrc1(const GCNSubtarget & ST) const24 uint64_t SIProgramInfo::getComputePGMRSrc1(const GCNSubtarget &ST) const {
25   uint64_t Reg = S_00B848_VGPRS(VGPRBlocks) | S_00B848_SGPRS(SGPRBlocks) |
26                  S_00B848_PRIORITY(Priority) | S_00B848_FLOAT_MODE(FloatMode) |
27                  S_00B848_PRIV(Priv) | S_00B848_DEBUG_MODE(DebugMode) |
28                  S_00B848_WGP_MODE(WgpMode) | S_00B848_MEM_ORDERED(MemOrdered);
29 
30   if (ST.hasDX10ClampMode())
31     Reg |= S_00B848_DX10_CLAMP(DX10Clamp);
32 
33   if (ST.hasIEEEMode())
34     Reg |= S_00B848_IEEE_MODE(IEEEMode);
35 
36   if (ST.hasRrWGMode())
37     Reg |= S_00B848_RR_WG_MODE(RrWgMode);
38 
39   return Reg;
40 }
41 
getPGMRSrc1(CallingConv::ID CC,const GCNSubtarget & ST) const42 uint64_t SIProgramInfo::getPGMRSrc1(CallingConv::ID CC,
43                                     const GCNSubtarget &ST) const {
44   if (AMDGPU::isCompute(CC)) {
45     return getComputePGMRSrc1(ST);
46   }
47   uint64_t Reg = S_00B848_VGPRS(VGPRBlocks) | S_00B848_SGPRS(SGPRBlocks) |
48                  S_00B848_PRIORITY(Priority) | S_00B848_FLOAT_MODE(FloatMode) |
49                  S_00B848_PRIV(Priv) | S_00B848_DEBUG_MODE(DebugMode);
50 
51   if (ST.hasDX10ClampMode())
52     Reg |= S_00B848_DX10_CLAMP(DX10Clamp);
53 
54   if (ST.hasIEEEMode())
55     Reg |= S_00B848_IEEE_MODE(IEEEMode);
56 
57   if (ST.hasRrWGMode())
58     Reg |= S_00B848_RR_WG_MODE(RrWgMode);
59 
60   switch (CC) {
61   case CallingConv::AMDGPU_PS:
62     Reg |= S_00B028_MEM_ORDERED(MemOrdered);
63     break;
64   case CallingConv::AMDGPU_VS:
65     Reg |= S_00B128_MEM_ORDERED(MemOrdered);
66     break;
67   case CallingConv::AMDGPU_GS:
68     Reg |= S_00B228_WGP_MODE(WgpMode) | S_00B228_MEM_ORDERED(MemOrdered);
69     break;
70   case CallingConv::AMDGPU_HS:
71     Reg |= S_00B428_WGP_MODE(WgpMode) | S_00B428_MEM_ORDERED(MemOrdered);
72     break;
73   default:
74     break;
75   }
76   return Reg;
77 }
78 
getComputePGMRSrc2() const79 uint64_t SIProgramInfo::getComputePGMRSrc2() const {
80   uint64_t Reg =
81       S_00B84C_SCRATCH_EN(ScratchEnable) | S_00B84C_USER_SGPR(UserSGPR) |
82       S_00B84C_TRAP_HANDLER(TrapHandlerEnable) |
83       S_00B84C_TGID_X_EN(TGIdXEnable) | S_00B84C_TGID_Y_EN(TGIdYEnable) |
84       S_00B84C_TGID_Z_EN(TGIdZEnable) | S_00B84C_TG_SIZE_EN(TGSizeEnable) |
85       S_00B84C_TIDIG_COMP_CNT(TIdIGCompCount) |
86       S_00B84C_EXCP_EN_MSB(EXCPEnMSB) | S_00B84C_LDS_SIZE(LdsSize) |
87       S_00B84C_EXCP_EN(EXCPEnable);
88 
89   return Reg;
90 }
91 
getPGMRSrc2(CallingConv::ID CC) const92 uint64_t SIProgramInfo::getPGMRSrc2(CallingConv::ID CC) const {
93   if (AMDGPU::isCompute(CC))
94     return getComputePGMRSrc2();
95 
96   return 0;
97 }
98