Searched refs:MACRO_TILE_ASPECT (Results 1 – 17 of 17) sorted by relevance
91 #define MACRO_TILE_ASPECT(x) ((x) << 18) macro430 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v6_0_tiling_mode_table_init()438 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v6_0_tiling_mode_table_init()446 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v6_0_tiling_mode_table_init()655 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); in gfx_v6_0_tiling_mode_table_init()663 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); in gfx_v6_0_tiling_mode_table_init()671 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); in gfx_v6_0_tiling_mode_table_init()679 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); in gfx_v6_0_tiling_mode_table_init()687 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); in gfx_v6_0_tiling_mode_table_init()695 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); in gfx_v6_0_tiling_mode_table_init()[all …]
2222 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v8_0_tiling_mode_table_init()2226 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v8_0_tiling_mode_table_init()2230 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v8_0_tiling_mode_table_init()2234 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v8_0_tiling_mode_table_init()2238 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v8_0_tiling_mode_table_init()2242 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v8_0_tiling_mode_table_init()2246 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v8_0_tiling_mode_table_init()2250 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v8_0_tiling_mode_table_init()2254 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v8_0_tiling_mode_table_init()2414 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v8_0_tiling_mode_table_init()[all …]
1168 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v7_0_tiling_mode_table_init()1172 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v7_0_tiling_mode_table_init()1176 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v7_0_tiling_mode_table_init()1180 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v7_0_tiling_mode_table_init()1184 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v7_0_tiling_mode_table_init()1188 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in gfx_v7_0_tiling_mode_table_init()1192 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | in gfx_v7_0_tiling_mode_table_init()1196 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v7_0_tiling_mode_table_init()1200 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v7_0_tiling_mode_table_init()1204 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in gfx_v7_0_tiling_mode_table_init()[all …]
200 # define MACRO_TILE_ASPECT(x) ((x) << 4) macro
1216 # define MACRO_TILE_ASPECT(x) ((x) << 18) macro
1919 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v8_0_crtc_do_set_base()
1947 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v6_0_crtc_do_set_base()
1998 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v10_0_crtc_do_set_base()
2040 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v11_0_crtc_do_set_base()
2534 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); in si_tiling_mode_table_init()2543 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); in si_tiling_mode_table_init()2552 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); in si_tiling_mode_table_init()2561 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); in si_tiling_mode_table_init()2570 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); in si_tiling_mode_table_init()2579 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); in si_tiling_mode_table_init()2588 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); in si_tiling_mode_table_init()2597 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); in si_tiling_mode_table_init()2606 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); in si_tiling_mode_table_init()2615 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); in si_tiling_mode_table_init()[all …]
2607 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in cik_tiling_mode_table_init()2611 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in cik_tiling_mode_table_init()2615 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in cik_tiling_mode_table_init()2619 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in cik_tiling_mode_table_init()2623 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | in cik_tiling_mode_table_init()2627 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | in cik_tiling_mode_table_init()2631 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | in cik_tiling_mode_table_init()2635 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in cik_tiling_mode_table_init()2639 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | in cik_tiling_mode_table_init()2643 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | in cik_tiling_mode_table_init()[all …]
1218 # define MACRO_TILE_ASPECT(x) ((x) << 18) macro
1272 # define MACRO_TILE_ASPECT(x) ((x) << 4) macro
2418 # define MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6) macro
2402 MACRO_TILE_ASPECT(mtaspect) | in evergreen_packet3_check()
1768 typedef enum MACRO_TILE_ASPECT { enum1773 } MACRO_TILE_ASPECT; typedef
3267 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in fill_plane_buffer_attributes()