Searched refs:mmCP_ME_CNTL (Results 1 – 15 of 15) sorted by relevance
/netbsd/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
H A D | polaris10_pwrvirus.h | 53 { 0x15000000, mmCP_ME_CNTL },
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/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/ |
H A D | gfx_6_0_d.h | 449 #define mmCP_ME_CNTL 0x21B6 macro
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H A D | gfx_7_0_d.h | 507 #define mmCP_ME_CNTL 0x21b6 macro
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H A D | gfx_7_2_d.h | 520 #define mmCP_ME_CNTL 0x21b6 macro
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H A D | gfx_8_0_d.h | 573 #define mmCP_ME_CNTL 0x21b6 macro
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H A D | gfx_8_1_d.h | 573 #define mmCP_ME_CNTL 0x21b6 macro
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/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
H A D | amdgpu_gfx_v7_0.c | 2445 WREG32(mmCP_ME_CNTL, 0); in gfx_v7_0_cp_gfx_enable() 2447 …WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_M… in gfx_v7_0_cp_gfx_enable() 4673 …WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MA… in gfx_v7_0_soft_reset()
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H A D | amdgpu_gfx_v6_0.c | 1960 WREG32(mmCP_ME_CNTL, 0); in gfx_v6_0_cp_gfx_enable() 1962 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | in gfx_v6_0_cp_gfx_enable()
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H A D | amdgpu_gfx_v10_0.c | 2396 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); in gfx_v10_0_cp_gfx_enable() 2405 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); in gfx_v10_0_cp_gfx_enable()
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H A D | amdgpu_gfx_v9_0.c | 3044 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); in gfx_v9_0_cp_gfx_enable() 3053 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); in gfx_v9_0_cp_gfx_enable()
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H A D | amdgpu_gfx_v8_0.c | 4123 u32 tmp = RREG32(mmCP_ME_CNTL); in gfx_v8_0_cp_gfx_enable() 4136 WREG32(mmCP_ME_CNTL, tmp); in gfx_v8_0_cp_gfx_enable()
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/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/ |
H A D | gc_9_0_offset.h | 194 #define mmCP_ME_CNTL … macro
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H A D | gc_9_2_1_offset.h | 188 #define mmCP_ME_CNTL … macro
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H A D | gc_9_1_offset.h | 194 #define mmCP_ME_CNTL … macro
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H A D | gc_10_1_0_offset.h | 2198 #define mmCP_ME_CNTL … macro
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