Searched refs:mmRLC_CNTL (Results 1 – 15 of 15) sorted by relevance
/netbsd/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
H A D | polaris10_pwrvirus.h | 51 { 0x00000000, mmRLC_CNTL },
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/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
H A D | amdgpu_gfx_v6_0.c | 2465 tmp = RREG32(mmRLC_CNTL); in gfx_v6_0_update_rlc() 2467 WREG32(mmRLC_CNTL, rlc); in gfx_v6_0_update_rlc() 2474 orig = data = RREG32(mmRLC_CNTL); in gfx_v6_0_halt_rlc() 2478 WREG32(mmRLC_CNTL, data); in gfx_v6_0_halt_rlc() 2488 WREG32(mmRLC_CNTL, 0); in gfx_v6_0_rlc_stop() 2496 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); in gfx_v6_0_rlc_start()
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H A D | amdgpu_gfx_v7_0.c | 3406 tmp = RREG32(mmRLC_CNTL); in gfx_v7_0_update_rlc() 3408 WREG32(mmRLC_CNTL, rlc); in gfx_v7_0_update_rlc() 3415 orig = data = RREG32(mmRLC_CNTL); in gfx_v7_0_halt_rlc() 3421 WREG32(mmRLC_CNTL, data); in gfx_v7_0_halt_rlc() 3479 WREG32(mmRLC_CNTL, 0); in gfx_v7_0_rlc_stop() 3495 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); in gfx_v7_0_rlc_start()
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H A D | amdgpu_gfx_v10_0.c | 1804 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); in gfx_v10_0_rlc_stop() 1807 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); in gfx_v10_0_rlc_stop() 2193 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); in gfx_v10_0_rlc_backdoor_autoload_enable() 4009 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); in gfx_v10_0_is_rlc_enabled()
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H A D | amdgpu_gfx_v8_0.c | 5549 rlc_setting = RREG32(mmRLC_CNTL); in gfx_v8_0_is_rlc_enabled() 5560 data = RREG32(mmRLC_CNTL); in gfx_v8_0_set_safe_mode() 5588 data = RREG32(mmRLC_CNTL); in gfx_v8_0_unset_safe_mode()
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H A D | amdgpu_gfx_v9_0.c | 4442 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); in gfx_v9_0_is_rlc_enabled()
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/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/ |
H A D | gfx_6_0_d.h | 1138 #define mmRLC_CNTL 0x30C0 macro
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H A D | gfx_7_0_d.h | 1242 #define mmRLC_CNTL 0x30c0 macro
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H A D | gfx_7_2_d.h | 1255 #define mmRLC_CNTL 0x30c0 macro
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H A D | gfx_8_0_d.h | 1344 #define mmRLC_CNTL 0xec00 macro
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H A D | gfx_8_1_d.h | 1347 #define mmRLC_CNTL 0xec00 macro
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/netbsd/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/ |
H A D | gc_9_0_offset.h | 5960 #define mmRLC_CNTL … macro
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H A D | gc_9_2_1_offset.h | 6146 #define mmRLC_CNTL … macro
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H A D | gc_9_1_offset.h | 6182 #define mmRLC_CNTL … macro
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H A D | gc_10_1_0_offset.h | 9270 #define mmRLC_CNTL … macro
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