/freebsd/sys/arm64/broadcom/genet/ |
H A D | if_genet.c | 491 val = RD4(sc, GENET_RBUF_CTRL); in gen_enable() 498 val = RD4(sc, GENET_UMAC_CMD); in gen_enable() 523 val = RD4(sc, GENET_UMAC_CMD); in gen_disable() 528 val = RD4(sc, GENET_UMAC_CMD); in gen_disable() 567 val = RD4(sc, GENET_TX_DMA_CTRL); in gen_dma_disable() 572 val = RD4(sc, GENET_RX_DMA_CTRL); in gen_dma_disable() 954 cmd = RD4(sc, GENET_UMAC_CMD); in gen_setup_rxfilter() 1647 val = RD4(sc, GENET_MDIO_CMD); in gen_miibus_readreg() 1678 val = RD4(sc, GENET_MDIO_CMD); in gen_miibus_writereg() 1681 val = RD4(sc, GENET_MDIO_CMD); in gen_miibus_writereg() [all …]
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/freebsd/sys/arm64/freescale/imx/clk/ |
H A D | imx_clk_gate.c | 41 #define RD4(_clk, off, val) \ macro 91 RD4(clk, sc->offset, ®); in imx_clk_gate_set_gate()
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H A D | imx_clk_mux.c | 45 #define RD4(_clk, off, val) \ macro 83 rv = RD4(clk, sc->offset, ®); in imx_clk_mux_init() 109 RD4(clk, sc->offset, ®); in imx_clk_mux_set_mux()
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/freebsd/sys/arm64/nvidia/tegra210/ |
H A D | tegra210_car.h | 33 #define RD4(sc, reg, val) CLKDEV_READ_4((sc)->clkdev, reg, val) macro
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H A D | tegra210_clk_per.c | 669 RD4(sc, sc->base_reg, ®); in periph_init() 710 RD4(sc, sc->base_reg, ®); in periph_set_mux() 741 RD4(sc, sc->base_reg, ®); in periph_recalc() 857 RD4(sc, get_enable_reg(sc->idx), &ena_reg); in pgate_init() 858 RD4(sc, get_reset_reg(sc->idx), &rst_reg); in pgate_init() 880 RD4(sc, base_reg, ®); in pgate_set_gate() 898 RD4(sc, base_reg, ®); in pgate_get_gate()
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H A D | tegra210_clk_pll.c | 603 RD4(sc, sc->base_reg, ®); in pll_enable() 616 RD4(sc, sc->base_reg, ®); in pll_disable() 688 RD4(sc, sc->base_reg, &val); in get_divisors() 758 RD4(sc, sc->base_reg, ®); in plle_enable() 763 RD4(sc, PLLE_AUX, ®); in plle_enable() 817 RD4(sc, PLLE_AUX, ®); in plle_enable() 1162 RD4(sc, PLLX_MISC_2, ®); in pllx_set_freq() 1167 RD4(sc, PLLX_MISC_2, ®); in pllx_set_freq() 1173 RD4(sc, PLLX_MISC_2, ®); in pllx_set_freq() 1196 RD4(sc, PLLX_MISC_2, ®); in pllx_set_freq() [all …]
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H A D | tegra210_clk_super.c | 149 RD4(sc, sc->base_reg, ®); in super_mux_init() 177 RD4(sc, sc->base_reg, ®); in super_mux_set_mux() 191 RD4(sc, sc->base_reg, &dummy); in super_mux_set_mux()
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H A D | tegra210_pmc.c | 234 reg = RD4(sc, PMC_PWRGATE_TOGGLE); in tegra210_pmc_set_powergate() 274 reg = RD4(sc, PMC_PWRGATE_STATUS); in tegra_powergate_remove_clamping() 295 reg = RD4(sc, PMC_CLAMP_STATUS); in tegra_powergate_remove_clamping() 310 reg = RD4(sc, PMC_PWRGATE_STATUS); in tegra_powergate_is_powered() 505 orig = RD4(sc, PMC_SCRATCH0); in tegra210_pmc_check_secure() 507 if (RD4(sc, PMC_SCRATCH0) == 0) { in tegra210_pmc_check_secure() 512 if (RD4(sc, PMC_SCRATCH0) == 0) { in tegra210_pmc_check_secure() 577 reg = RD4(sc, PMC_CNTRL); in tegra210_pmc_attach() 582 reg = RD4(sc, PMC_CNTRL); in tegra210_pmc_attach() 590 reg = RD4(sc, PMC_CNTRL); in tegra210_pmc_attach() [all …]
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H A D | tegra210_xusbpadctl.c | 1007 reg = RD4(sc, XUSB_PADCTL_SS_PORT_MAP); in usb3_port_init() 1051 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); in usb3_port_init() 1056 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); in usb3_port_init() 1061 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); in usb3_port_init() 1079 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); in pcie_enable() 1091 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); in pcie_disable() 1111 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); in sata_enable() 1123 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); in sata_disable() 1275 reg = RD4(sc, XUSB_PADCTL_USB2_PORT_CAP); in usb2_enable() 1379 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); in pad_common_enable() [all …]
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/freebsd/sys/arm64/qoriq/clk/ |
H A D | qoriq_clk_pll.c | 52 #define RD4(_clk, offset, val) \ macro 78 RD4(clk, sc->offset, &mul); in qoriq_clk_pll_recalc_freq()
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/freebsd/sys/arm64/qoriq/ |
H A D | qoriq_gpio_pic.c | 67 #define RD4(sc, off) bus_read_4((sc)->base.sc_mem, (off)) macro 79 reg = RD4(sc, GPIO_GPIMR); in qoriq_gpio_pic_set_intr() 107 status = RD4(sc, GPIO_GPIER); in qoriq_gpio_pic_intr() 108 status &= RD4(sc, GPIO_GPIMR); in qoriq_gpio_pic_intr() 248 reg = RD4(sc, GPIO_GPICR); in qoriq_gpio_pic_setup_intr()
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H A D | qoriq_therm.c | 204 RD4(struct qoriq_therm_softc *sc, bus_size_t addr) in RD4() function 221 val = RD4(sc, TMU_TRITSR(sensor->site_id)); in qoriq_therm_read_temp() 399 sc->ver = (RD4(sc, TMU_VERSION) >> 8) & 0xFF; in qoriq_therm_attach() 424 RD4(sc, TMU_TMR); in qoriq_therm_attach()
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/freebsd/sys/arm64/rockchip/ |
H A D | rk_pcie_phy.c | 97 #define RD4(sc, reg) SYSCON_READ_4((sc)->syscon, (reg)) macro 110 RD4(sc, GRF_SOC_CON8); in cfg_write() 114 RD4(sc, GRF_SOC_CON8); in cfg_write() 117 RD4(sc, GRF_SOC_CON8); in cfg_write() 127 RD4(sc, GRF_SOC_CON8); in cfg_read() 129 val = RD4(sc, GRF_SOC_STATUS1); in cfg_read()
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H A D | rk_tsadc.c | 101 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) macro 475 val = RD4(sc, TSADC_INT_EN); in tsadc_init_tsensor() 489 val = RD4(sc, TSADC_AUTO_CON); in tsadc_init_tsensor() 496 val = RD4(sc, TSADC_INT_EN); in tsadc_init_tsensor() 574 val = RD4(sc, TSADC_DATA(sensor->channel)); in tsadc_read_temp() 582 __func__, RD4(sc, TSADC_USER_CON), RD4(sc, TSADC_AUTO_CON), in tsadc_read_temp() 583 RD4(sc, TSADC_COMP_INT(sensor->channel)), in tsadc_read_temp() 584 RD4(sc, TSADC_COMP_SHUT(sensor->channel))); in tsadc_read_temp() 671 val = RD4(sc, TSADC_INT_PD); in tsadc_intr() 810 val = RD4(sc, TSADC_AUTO_CON); in tsadc_attach()
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H A D | rk_usbphy.c | 68 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) macro
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/freebsd/sys/dev/cadence/ |
H A D | if_cgem.c | 251 uint32_t low = RD4(sc, CGEM_SPEC_ADDR_LOW(i)); in cgem_get_mac() 384 queue_mask = (RD4(sc, CGEM_DESIGN_CFG6) & in cgem_null_qs() 896 n = RD4(sc, CGEM_SINGLE_COLL_FRAMES); in cgem_poll_hw_stats() 899 n = RD4(sc, CGEM_MULTI_COLL_FRAMES); in cgem_poll_hw_stats() 902 n = RD4(sc, CGEM_EXCESSIVE_COLL_FRAMES); in cgem_poll_hw_stats() 905 n = RD4(sc, CGEM_LATE_COLL); in cgem_poll_hw_stats() 990 istatus = RD4(sc, CGEM_INTR_STAT); in cgem_intr() 1004 RD4(sc, CGEM_RX_STAT)); in cgem_intr() 1038 switch (RD4(sc, CGEM_DESIGN_CFG1) & in cgem_reset() 1290 RD4(sc, CGEM_DMA_CFG) | in cgem_ioctl() [all …]
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/freebsd/sys/dev/clk/ |
H A D | clk_div.c | 41 #define RD4(_clk, off, val) \ macro 124 rv = RD4(clk, sc->offset, ®); in clknode_div_init() 229 RD4(clk, sc->offset, ®); in clknode_div_set_freq()
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H A D | clk_gate.c | 41 #define RD4(_clk, off, val) \ macro 95 RD4(clk, sc->offset, ®); in clknode_gate_set_gate() 109 rv = RD4(clk, sc->offset, ®); in clknode_gate_get_gate()
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H A D | clk_mux.c | 41 #define RD4(_clk, off, val) \ macro 80 rv = RD4(clk, sc->offset, ®); in clknode_mux_init() 106 RD4(clk, sc->offset, ®); in clknode_mux_set_mux()
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/freebsd/sys/dev/clk/rockchip/ |
H A D | rk_clk_fract.c | 40 #define RD4(_clk, off, val) \ macro 145 RD4(clk, sc->offset, ®); in rk_clk_fract_init() 168 RD4(clk, sc->gate_offset, &val); in rk_clk_fract_set_gate()
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H A D | rk_clk_gate.c | 41 #define RD4(_clk, off, val) \ macro 80 rv = RD4(clk, sc->offset, ®); in rk_clk_gate_init() 107 RD4(clk, sc->offset, ®); in rk_clk_gate_set_gate()
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H A D | rk_clk_mux.c | 48 #define RD4(_clk, off, val) \ macro 127 rv = RD4(clk, sc->offset, ®); in rk_clk_mux_init() 158 RD4(clk, sc->offset, ®); in rk_clk_mux_set_mux()
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/freebsd/sys/dev/eqos/ |
H A D | if_eqos.c | 126 addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS); in eqos_miibus_readreg() 159 addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS); in eqos_miibus_writereg() 186 reg = RD4(sc, GMAC_MAC_CONFIGURATION); in eqos_miibus_statchg() 461 val = RD4(sc, GMAC_DMA_MODE); in eqos_reset() 508 val = RD4(sc, GMAC_DMA_CHAN0_CONTROL); in eqos_init() 543 val = RD4(sc, GMAC_MAC_RX_FLOW_CTRL); in eqos_init() 552 val = RD4(sc, GMAC_MAC_CONFIGURATION); in eqos_init() 639 val = RD4(sc, GMAC_MAC_CONFIGURATION); in eqos_stop() 861 RD4(sc, GMAC_DMA_CHAN0_STATUS)); in eqos_intr() 962 val = RD4(sc, GMAC_DMA_SYSBUS_MODE); in eqos_axi_configure() [all …]
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/freebsd/sys/dev/ffec/ |
H A D | if_ffec.c | 482 mibc = RD4(sc, FEC_MIBC_REG); in ffec_clear_stats() 532 RD4(sc, FEC_RMON_R_CRC_ALIGN) + RD4(sc, FEC_RMON_R_UNDERSIZE) + in ffec_harvest_stats() 533 RD4(sc, FEC_RMON_R_OVERSIZE) + RD4(sc, FEC_RMON_R_FRAG) + in ffec_harvest_stats() 534 RD4(sc, FEC_RMON_R_JAB) + RD4(sc, FEC_IEEE_R_DROP)); in ffec_harvest_stats() 541 RD4(sc, FEC_RMON_T_CRC_ALIGN) + RD4(sc, FEC_RMON_T_UNDERSIZE) + in ffec_harvest_stats() 542 RD4(sc, FEC_RMON_T_OVERSIZE) + RD4(sc, FEC_RMON_T_FRAG) + in ffec_harvest_stats() 543 RD4(sc, FEC_RMON_T_JAB)); in ffec_harvest_stats() 949 palr = RD4(sc, FEC_PALR_REG); in ffec_get_hwaddr() 1229 regval = RD4(sc, FEC_MIBC_REG); in ffec_init_locked() 1251 regval = RD4(sc, FEC_ECR_REG); in ffec_init_locked() [all …]
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/freebsd/sys/dev/hwpmc/ |
H A D | pmu_dmc620.c | 69 #define RD4(sc, r) bus_read_4((sc)->sc_res[0], (r)) macro 71 #define MD4(sc, r, c, s) WR4((sc), (r), RD4((sc), (r)) & ~(c) | (s)) 87 val = RD4(sc, DMC620_REG(cntr, reg)); in pmu_dmc620_rd4() 215 clkdiv2_stat = RD4(sc, DMC620_OVERFLOW_STATUS_CLKDIV2); in pmu_dmc620_counter_overflow_intr() 216 clk_stat = RD4(sc, DMC620_OVERFLOW_STATUS_CLK); in pmu_dmc620_counter_overflow_intr() 222 sc->sc_saved_control[i] = RD4(sc, DMC620_REG(i, in pmu_dmc620_counter_overflow_intr()
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