world/kernel: Use the powerof2() macro in various places.

kernel: Remove numerous #include <sys/thread2.h>.

Most of them were added when we converted spl*() calls to
crit_enter()/crit_exit(), almost 14 years ago. We can now
remove a good chunk of them agai

kernel: Remove numerous #include <sys/thread2.h>.

Most of them were added when we converted spl*() calls to
crit_enter()/crit_exit(), almost 14 years ago. We can now
remove a good chunk of them again for where crit_*() are
no longer used.

I had to adjust some files that were relying on thread2.h
or headers that it includes coming in via other headers
that it was removed from.

show more ...

x86_64/ioapic: Make sure that legacy IRQ only appears on one CPU.

The legacy IRQ lookup assumes only one CPU has a given legacy IRQ.

On system w/ large number of IOAPIC, GSI96 could be mapped to IR

x86_64/ioapic: Make sure that legacy IRQ only appears on one CPU.

The legacy IRQ lookup assumes only one CPU has a given legacy IRQ.

On system w/ large number of IOAPIC, GSI96 could be mapped to IRQ17
on CPU0 (since IRQ96 is used by SYSCALL), while GSI17 is mapped to
IRQ17 on another CPU. This breaks later IRQ lookup.

Reported-by: Imre Vadasz
Tested-by: Imre Vadasz

show more ...

Revert "kernel - Spread IPIs out to more priority levels"

This commit seems to be causing a performance regression on VMs.
Since it didn't fix a particular bug (was just supposed to make
things more

Revert "kernel - Spread IPIs out to more priority levels"

This commit seems to be causing a performance regression on VMs.
Since it didn't fix a particular bug (was just supposed to make
things more robust), revert it for now.

Reported-by: tkusumi

This reverts commit f240042b9f9bcfdacd70499659fcc5f55d5e49ab.

show more ...

kernel - Spread IPIs out to more priority levels

* Due to the brandamaged way the LAPIC queues received IPIs, each
priority level (the top 4 bits of the 8 bit vector) has a 2-entry
FIFO. Bring

kernel - Spread IPIs out to more priority levels

* Due to the brandamaged way the LAPIC queues received IPIs, each
priority level (the top 4 bits of the 8 bit vector) has a 2-entry
FIFO. Bring in comments from FreeBSD on how this works.

* Change our IPI vectors which previously used 2 priority levels to now
use 3 priority levels. Each source is generally limited by an atomic
op to avoid multi-queueing and hopefully that means the above LAPIC hw
queue will never refuse to accept an IPI.

IPIQ and TIMER use group 1

INVLTLB (and INVLPG) uses group 2

SNIFF, CPUSTOP, and SPURIOUSINT use group 3

* Reduces the number of vectors available per cpu by 16, but shouldn't
present that big a problem.

show more ...

kernel - Reduce BSS size to fix loader initrd problem

* kernel + modules + initrd.img (unpacked) exceeded the 63MB the loader has
available for load-time data.

* Top hogs are mainly in BSS. Make

kernel - Reduce BSS size to fix loader initrd problem

* kernel + modules + initrd.img (unpacked) exceeded the 63MB the loader has
available for load-time data.

* Top hogs are mainly in BSS. Make intr_info_ary and pcpu_sysctl
kmalloc after boot instead of BSS as a temporary fix.

335872 ifnet_threads
335872 netisr_cpu
339968 dummy_pcpu
344064 bsd4_pcpu
344064 stoppcbs
346112 softclock_pcpu_ary
538624 cpu_topology_nodes
755712 dfly_pcpu
786432 icu_irqmaps
958464 map_entry_init
1048576 idt_arr
1064960 pcpu_sysctl <---- now kmallocd
1179648 ioapic_irqmaps <---- (used too early, cannot be kmallocd)
5242880 intr_info_ary <---- now kmallocd

* Should fix loader issues when trying to use initrd.img[.gz] for now.

Reported-by: Valheru

show more ...

x86_64/ioapic: Enable GSI target CPU auto-balance by default

The original bug, which prevented GSI target CPU auto-balance, probably
was fixed by 902419bf6d9fd0f80afc9d07cd4b3e99d20f23ca.

ioapic: Relocate IRQ if it hits SYSCALL entry

The system hitting the "unused IRQ assertion" has 5x24 pin IOAPICs

Reported-by: ruse39

kernel: Move sys/dev/acpica5 to sys/dev/acpica.

The 5 used to indicate that it was imported from FreeBSD 5 but that
doesn't matter anymore.

In-discussion-with: sephe

ioapic/x86_64: Allow GSI > 191

Some BIOSes seem to assume that all 256 IDT vectors could be used,
while we limit the available IDT vectors percpu to 192. Find an
unused IRQ for these GSIs, if this

ioapic/x86_64: Allow GSI > 191

Some BIOSes seem to assume that all 256 IDT vectors could be used,
while we limit the available IDT vectors percpu to 192. Find an
unused IRQ for these GSIs, if this ever happens.

Reported-by: thowe on EFnet #dragonflybsd

show more ...

MachIntr: Add two methods to find IRQ

- Find IRQ conforming to the specified trigger and polarity, if it was
configured.
- Find IRQ by GSI, the located IRQ must conform to the specified trigger

MachIntr: Add two methods to find IRQ

- Find IRQ conforming to the specified trigger and polarity, if it was
configured.
- Find IRQ by GSI, the located IRQ must conform to the specified trigger
and polarity if it was configured.

show more ...

kernel: Remove newlines from the panic messages that have one.

panic() itself will add a newline.

ioapic_abi/x86_64: Implement MSI-X alloc/release

MachIntrABI: intr_{config,cpuid} -> legacy_intr_{config,cpuid}

So these two functions will not be misused on MSI. No functional changes

ioapic_abi: More consistent function name w/ legacy interrupt

No functional changes

x86_64: LINE interrupt -> LEGACY interrupt

ioapic_abi/x86_64: Remove no longer applied warning

While I'm here, strip blank lines

msi/pci: Adjust pci_alloc_msi method interface

- The requested number of MSI messages is no longer adjusted in
pci_alloc_msi_method(), instead, caller should adjust it.
- rids of the MSI SYS_RES_I

msi/pci: Adjust pci_alloc_msi method interface

- The requested number of MSI messages is no longer adjusted in
pci_alloc_msi_method(), instead, caller should adjust it.
- rids of the MSI SYS_RES_IRQ are explicitly returned to caller,
instead of letting caller fill them based on the implied rules.
- MSI messages' target CPU auto-selection.
- Intead of reallocation using reduced number of MSI messages,
we try to allocate the requested amount of MSI messages on
different CPUs, if the desired CPU does not have enough vectors.
- The requested amount of MSI messages must be sane.

show more ...

x86_64/msi: Add hw.ioapic.msi_start tunable

This is mainly used to test MSI allocation over the whole valid
hardware interrupt space.

x86_64: Add MSI support for IOAPIC MachIntrABI

x86_64: Per-cpu IDT

x86_64/MachintrABI: Use low-level INTR{EN,DIS} in intr_{setup,teardown}

intr_{setup,teardown} have already done enough verification for the
'intr' parameter

x86_64/ioapic_abi: Augment intr_{setup,teardown} w/ assertions

x86_64/ioapic_abi: Augment intr_disable/intr_enable w/ assertions

x86_64/ioapic: Always allow user to specify GSI's target CPU

Even if interrupt automatic load balance is disable we still should
obey the explicit GSI target CPU configuration.