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Revision tags: v5.18-rc5, v5.18-rc4, v5.18-rc3, v5.18-rc2, v5.18-rc1, v5.17, v5.17-rc8, v5.17-rc7, v5.17-rc6, v5.17-rc5, v5.17-rc4, v5.17-rc3, v5.17-rc2, v5.17-rc1, v5.16, v5.16-rc8, v5.16-rc7, v5.16-rc6, v5.16-rc5, v5.16-rc4, v5.16-rc3, v5.16-rc2, v5.16-rc1, v5.15, v5.15-rc7, v5.15-rc6, v5.15-rc5, v5.15-rc4, v5.15-rc3, v5.15-rc2, v5.15-rc1, v5.14, v5.14-rc7, v5.14-rc6, v5.14-rc5, v5.14-rc4, v5.14-rc3, v5.14-rc2, v5.14-rc1, v5.13, v5.13-rc7, v5.13-rc6, v5.13-rc5, v5.13-rc4, v5.13-rc3, v5.13-rc2, v5.13-rc1, v5.12, v5.12-rc8, v5.12-rc7, v5.12-rc6, v5.12-rc5, v5.12-rc4, v5.12-rc3, v5.12-rc2, v5.12-rc1-dontuse, v5.11, v5.11-rc7, v5.11-rc6, v5.11-rc5, v5.11-rc4, v5.11-rc3, v5.11-rc2, v5.11-rc1, v5.10, v5.10-rc7, v5.10-rc6, v5.10-rc5, v5.10-rc4, v5.10-rc3, v5.10-rc2, v5.10-rc1, v5.9, v5.9-rc8, v5.9-rc7, v5.9-rc6, v5.9-rc5, v5.9-rc4, v5.9-rc3, v5.9-rc2, v5.9-rc1, v5.8, v5.8-rc7, v5.8-rc6, v5.8-rc5, v5.8-rc4, v5.8-rc3, v5.8-rc2, v5.8-rc1, v5.7, v5.7-rc7, v5.7-rc6, v5.7-rc5, v5.7-rc4, v5.7-rc3, v5.7-rc2, v5.7-rc1, v5.6, v5.6-rc7, v5.6-rc6, v5.6-rc5, v5.6-rc4, v5.6-rc3, v5.6-rc2, v5.6-rc1, v5.5, v5.5-rc7, v5.5-rc6, v5.5-rc5, v5.5-rc4, v5.5-rc3, v5.5-rc2, v5.5-rc1, v5.4, v5.4-rc8, v5.4-rc7 |
| #
6973886a |
| 07-Nov-2019 |
Green Wan <green.wan@sifive.com> |
dmaengine: sf-pdma: add platform DMA support for HiFive Unleashed A00
Add PDMA driver, sf-pdma, to enable DMA engine on HiFive Unleashed
Rev A00 board.
- Implement dmaengine APIs, support MEM_TO_M
dmaengine: sf-pdma: add platform DMA support for HiFive Unleashed A00
Add PDMA driver, sf-pdma, to enable DMA engine on HiFive Unleashed
Rev A00 board.
- Implement dmaengine APIs, support MEM_TO_MEM async copy.
- Tested by DMA Test client
- Supports 4 channels DMA, each channel has 1 done and 1 err
interrupt connected to platform-level interrupt controller (PLIC).
- Depends on DMA_ENGINE and DMA_VIRTUAL_CHANNELS
The datasheet is here:
https://static.dev.sifive.com/FU540-C000-v1.0.pdf
Follow the DMAengine controller doc,
"./Documentation/driver-api/dmaengine/provider.rst" to implement DMA
engine. And use the dma test client in doc,
"./Documentation/driver-api/dmaengine/dmatest.rst", to test.
Each DMA channel has separate HW regs and support done and error ISRs.
4 channels share 1 done and 1 err ISRs. There's no expander/arbitrator
in DMA HW.
------ ------
| |--< done 23 >--|ch 0|
| |--< err 24 >--| | (dma0chan0)
| | ------
| | ------
| |--< done 25 >--|ch 1|
| |--< err 26 >--| | (dma0chan1)
|PLIC| ------
| | ------
| |--< done 27 >--|ch 2|
| |--< err 28 >--| | (dma0chan2)
| | ------
| | ------
| |--< done 29 >--|ch 3|
| |--< err 30 >--| | (dma0chan3)
------ ------
Signed-off-by: Green Wan <green.wan@sifive.com>
Link: https://lore.kernel.org/r/20191107084955.7580-4-green.wan@sifive.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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