#
1267f722 |
| 26-Jan-2024 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: Use refcount_t for reference counting
mlxsw driver uses 'unsigned int' for reference counters in several structures. Instead, use refcount_t type which allows us to catch overflow and underfl
mlxsw: Use refcount_t for reference counting
mlxsw driver uses 'unsigned int' for reference counters in several structures. Instead, use refcount_t type which allows us to catch overflow and underflow issues. Change the type of the counters and use the appropriate API.
Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Petr Machata <petrm@nvidia.com> Reviewed-by: Simon Horman <horms@kernel.org> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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#
9793a5a9 |
| 11-Aug-2023 |
Ido Schimmel <idosch@nvidia.com> |
mlxsw: spectrum: Stop ignoring learning notifications from redirected traffic
As explained in the previous patch, with the ignore action prepended to the redirect action, it is not longer possible f
mlxsw: spectrum: Stop ignoring learning notifications from redirected traffic
As explained in the previous patch, with the ignore action prepended to the redirect action, it is not longer possible for redirected traffic to generate learning notifications.
Therefore, remove the workaround that was added in commit 577fa14d2100 ("mlxsw: spectrum: Do not process learned records with a dummy FID") as it is no longer needed.
Signed-off-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Petr Machata <petrm@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
a76ca8af |
| 08-Aug-2023 |
Petr Machata <petrm@nvidia.com> |
mlxsw: Set port STP state on bridge enslavement
When the first port joins a LAG that already has a bridge upper, an instance of struct mlxsw_sp_bridge_port is created for the LAG to keep track of it
mlxsw: Set port STP state on bridge enslavement
When the first port joins a LAG that already has a bridge upper, an instance of struct mlxsw_sp_bridge_port is created for the LAG to keep track of it as a bridge port. The bridge_port's STP state is initialized to BR_STATE_DISABLED. This made sense previously, because mlxsw would only ever allow a port to join a LAG if the LAG had no uppers. Thus if a bridge_port was instantiated, it must have been because the LAG as such is joining a bridge, and the STP state is correspondingly disabled.
However as of commit 2c5ffe8d7226 ("mlxsw: spectrum: Permit enslavement to netdevices with uppers"), mlxsw allows a port to join a LAG that is already a member of a bridge. The STP state may be different than disabled in that case. Initialize it properly by querying the actual state.
This bug may cause an issue as traffic on ports attached to a bridged LAG gets dropped on ingress with discard_ingress_general counter bumped.
Fixes: c6514f3627a0 ("Merge branch 'mlxsw-enslavement'") Signed-off-by: Petr Machata <petrm@nvidia.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: Simon Horman <horms@kernel.org> Link: https://lore.kernel.org/r/39f4a5781050866b4132f350d7d8cf7ab23ea070.1691498735.git.petrm@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
99ecd6d0 |
| 08-Aug-2023 |
Ruan Jinjie <ruanjinjie@huawei.com> |
mlxsw: spectrum_switchdev: Use is_zero_ether_addr() instead of ether_addr_equal()
Use is_zero_ether_addr() instead of ether_addr_equal() to check if the ethernet address is all zeros.
Signed-off-by
mlxsw: spectrum_switchdev: Use is_zero_ether_addr() instead of ether_addr_equal()
Use is_zero_ether_addr() instead of ether_addr_equal() to check if the ethernet address is all zeros.
Signed-off-by: Ruan Jinjie <ruanjinjie@huawei.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Link: https://lore.kernel.org/r/20230808133528.4083501-1-ruanjinjie@huawei.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
1ae489ab |
| 27-Jul-2023 |
Petr Machata <petrm@nvidia.com> |
mlxsw: spectrum_switchdev: Use tracker helpers to hold & put netdevices
Using the tracking helpers makes it easier to debug netdevice refcount imbalances when CONFIG_NET_DEV_REFCNT_TRACKER is enable
mlxsw: spectrum_switchdev: Use tracker helpers to hold & put netdevices
Using the tracking helpers makes it easier to debug netdevice refcount imbalances when CONFIG_NET_DEV_REFCNT_TRACKER is enabled.
Convert dev_hold() / dev_put() to netdev_hold() / netdev_put() in the switchdev module.
Signed-off-by: Petr Machata <petrm@nvidia.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: Eric Dumazet <edumazet@google.com> Link: https://lore.kernel.org/r/774c3d7b5b0231f1435df2ec9dd660192e382756.1690471774.git.petrm@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
31618b22 |
| 19-Jul-2023 |
Petr Machata <petrm@nvidia.com> |
mlxsw: spectrum_router: Replay IP NETDEV_UP on device enslavement
Enslaving of front panel ports (and their uppers) to netdevices that already have uppers is currently forbidden. When this is permit
mlxsw: spectrum_router: Replay IP NETDEV_UP on device enslavement
Enslaving of front panel ports (and their uppers) to netdevices that already have uppers is currently forbidden. When this is permitted, any uppers with IP addresses need to have the NETDEV_UP inetaddr event replayed, so that any RIFs are created.
Signed-off-by: Petr Machata <petrm@nvidia.com> Reviewed-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
ec4643ca |
| 19-Jul-2023 |
Petr Machata <petrm@nvidia.com> |
mlxsw: spectrum_switchdev: Replay switchdev objects on port join
Currently it never happens that a netdevice that is already a bridge slave would suddenly become mlxsw upper. The only case where thi
mlxsw: spectrum_switchdev: Replay switchdev objects on port join
Currently it never happens that a netdevice that is already a bridge slave would suddenly become mlxsw upper. The only case where this might be possible as far as mlxsw is concerned, is with LAG netdevices. But if a LAG has any upper (e.g. is enslaved), enlaving mlxsw port to that LAG is forbidden. Thus the only way to install a LAG between a bridge and a mlxsw port is by first enslaving the port to the LAG, and then enslaving that LAG to a bridge. At that point there are no bridge objects (such as port VLANs) to replay. Those are added afterwards, and notified as they are created. This holds even for the PVID.
However in the following patches, the requirement that ports be only enslaved to masters without uppers, is going to be relaxed. It will therefore be necessary to replay the existing bridge objects. Without this replay, e.g. the mlxsw bridge_port_vlan objects are not instantiated, which causes issues later, as a lot of code relies on their presence.
To that end, add a new notifier block whose sole role is to filter out events related to the one relevant upper, and forward those to the existing switchdev notifier block. Pass the new notifier block to switchdev_bridge_port_offload() when the bridge port is created.
Signed-off-by: Petr Machata <petrm@nvidia.com> Reviewed-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
a5b52692 |
| 13-Jul-2023 |
Petr Machata <petrm@nvidia.com> |
mlxsw: spectrum_switchdev: Manage RIFs on PVID change
Currently, mlxsw has several shortcomings with regards to RIF handling due to PVID changes:
- In order to cause RIF for a bridge device to be c
mlxsw: spectrum_switchdev: Manage RIFs on PVID change
Currently, mlxsw has several shortcomings with regards to RIF handling due to PVID changes:
- In order to cause RIF for a bridge device to be created, the user is expected first to set PVID, then to add an IP address. The reverse ordering is disallowed, which is not very user-friendly.
- When such bridge gets a VLAN upper whose VID was the same as the existing PVID, and this VLAN netdevice gets an IP address, a RIF is created for this netdevice. The new RIF is then assigned to the 802.1Q FID for the given VID. This results in a working configuration. However, then, when the VLAN netdevice is removed again, the RIF for the bridge itself is never reassociated to the VLAN.
- PVID cannot be changed once the bridge has uppers. Presumably this is because the driver does not manage RIFs properly in face of PVID changes. However, as the previous point shows, it is still possible to get into invalid configurations.
In this patch, add the logic necessary for creation of a RIF as a result of PVID change. Moreover, when a VLAN upper is created whose VID matches lower PVID, do not create RIF for this netdevice.
These changes obviate the need for ordering of IP address additions and PVID configuration, so stop forbidding addition of an IP address to a PVID-less bridge. Instead, bail out quietly. Also stop preventing PVID changes when the bridge has uppers.
Signed-off-by: Petr Machata <petrm@nvidia.com> Reviewed-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
352be882 |
| 13-Jul-2023 |
Petr Machata <petrm@nvidia.com> |
mlxsw: spectrum_switchdev: Pass extack to mlxsw_sp_br_ban_rif_pvid_change()
Currently the reason for rejection of PVID manipulation is dumped to syslog, and a generic -EBUSY is returned to the users
mlxsw: spectrum_switchdev: Pass extack to mlxsw_sp_br_ban_rif_pvid_change()
Currently the reason for rejection of PVID manipulation is dumped to syslog, and a generic -EBUSY is returned to the userspace. But switchdev_handle_port_obj_add(), through which we get to mlxsw_sp_port_vlans_add(), handles extack just fine, and we can pass the message this way.
This improves visibility into reasons why the request to change PVID was rejected. Before the change:
# bridge vlan add dev br vid 2 self pvid untagged RTNETLINK answers: Device or resource busy (plus a syslog line)
After the change:
# bridge vlan add dev br vid 2 self pvid untagged Error: mlxsw_spectrum: Can't change PVID, it's used by router interface.
Note that this particular error message is going away in the following patches. However the ability to pass error messages through extack will be useful more broadly for communicating in particular reasons why a RIF failed to be created.
Signed-off-by: Petr Machata <petrm@nvidia.com> Reviewed-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
30f5312d |
| 11-Nov-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: Avoid warnings when not offloaded FDB entry with IPv6 is removed
FDB entries that perform VXLAN encapsulation with an IPv6 underlay hold a reference on a resource - the KVDL entry where the I
mlxsw: Avoid warnings when not offloaded FDB entry with IPv6 is removed
FDB entries that perform VXLAN encapsulation with an IPv6 underlay hold a reference on a resource - the KVDL entry where the IPv6 underlay destination IP is stored. For that, the driver maintains two hash tables: 1. Maps IPv6 to KVDL index 2. Maps {MAC, FID index} to IPv6 address
When a FDB entry is removed, the second table is used to find the relevant IPv6 address and the first table is used to remove the reference count and free the index if is not used anymore.
In order for a packet to be forwarded to a single remote VTEP, FDB entries need to be configured at both the bridge and VXLAN devices' FDB tables. Both entries are squashed into one {MAC, VLAN/VNI} -> IP entry in the hardware. Therefore, in case one entry is removed, the entry will be removed from the hardware and the remaining entry will be unmarked with 'offload' flag since it is not offloaded anymore.
For example, the two FDB entries should be added to allow packets to be forwarded via vx10: $ bridge fdb add dev vx10 aa:bb:cc:dd:ee:ff self static dst 2001:db8:5::1 $ bridge fdb add dev vx10 aa:bb:cc:dd:ee:ff master static vlan 10
When one entry will be removed, the second one will not be offloaded anymore. When the first entry (in VXLAN FDB) will be removed / will not be offloaded anymore, the two mappings in IPv6 hash tables will be removed.
In case that the second entry is removed before the first one, unexpected warnings[1][2] will be shown in user space as a result of removing the first entry. The issue is that not offloaded entry is removed, the driver tries to search the relevant entries in the hash tables, does not find them and therefore warns.
Do not handle removing of not offloaded VXLAN FDB entries, as they were already removed when the offload flag was removed.
[1]: WARNING: CPU: 1 PID: 239 at drivers/net/ethernet/mellanox/mlxsw/spectrum_nve.c:914 mlxsw_sp_nve_ipv6_addr_map_del+0x6b/0x80 [mlxsw_spectrum] ... Hardware name: Mellanox Technologies Ltd. Mellanox switch/Mellanox switch, BIOS 4.6.5 05/21/2015 Workqueue: mlxsw_core_ordered mlxsw_sp_switchdev_vxlan_fdb_event_work [mlxsw_spectrum] RIP: 0010:mlxsw_sp_nve_ipv6_addr_map_del+0x6b/0x80 [mlxsw_spectrum] ... Call Trace: <TASK> mlxsw_sp_port_fdb_tunnel_uc_op+0x6cf/0x7b0 [mlxsw_spectrum] mlxsw_sp_switchdev_vxlan_fdb_event_work+0x17c/0x420 [mlxsw_spectrum] ? finish_task_switch.isra.0+0x8c/0x290 process_one_work+0x1cd/0x390 worker_thread+0x48/0x3c0 ? process_one_work+0x390/0x390 kthread+0xe0/0x110 ? kthread_complete_and_exit+0x20/0x20 ret_from_fork+0x1f/0x30 </TASK>
[2]: WARNING: CPU: 0 PID: 239 at drivers/net/ethernet/mellanox/mlxsw/spectrum.c:3035 mlxsw_sp_ipv6_addr_put+0x142/0x220 [mlxsw_spectrum] ... Hardware name: Mellanox Technologies Ltd. Mellanox switch/Mellanox switch, BIOS 4.6.5 05/21/2015 Workqueue: mlxsw_core_ordered mlxsw_sp_switchdev_vxlan_fdb_event_work [mlxsw_spectrum] RIP: 0010:mlxsw_sp_ipv6_addr_put+0x142/0x220 [mlxsw_spectrum] ... Call Trace: <TASK> ? mlxsw_sp_port_fdb_tun_uc_op6_sfd_write+0x5c1/0x610 [mlxsw_spectrum] mlxsw_sp_port_fdb_tunnel_uc_op+0x6ec/0x7b0 [mlxsw_spectrum] mlxsw_sp_switchdev_vxlan_fdb_event_work+0x17c/0x420 [mlxsw_spectrum] ? finish_task_switch.isra.0+0x8c/0x290 process_one_work+0x1cd/0x390 worker_thread+0x48/0x3c0 ? process_one_work+0x390/0x390 kthread+0xe0/0x110 ? kthread_complete_and_exit+0x20/0x20 ret_from_fork+0x1f/0x30 </TASK>
Fixes: 0860c7641634 ("mlxsw: spectrum_nve: Keep track of IPv6 addresses used by FDB entries") Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Petr Machata <petrm@nvidia.com> Link: https://lore.kernel.org/r/c186de8cbd28e3eb661e06f31f7f2f2dff30020f.1668184350.git.petrm@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
25ed8088 |
| 08-Nov-2022 |
Ido Schimmel <idosch@nvidia.com> |
mlxsw: spectrum_switchdev: Add locked bridge port support
Add locked bridge port support by reacting to changes in the 'BR_PORT_LOCKED' flag. When set, enable security checks on the local port via t
mlxsw: spectrum_switchdev: Add locked bridge port support
Add locked bridge port support by reacting to changes in the 'BR_PORT_LOCKED' flag. When set, enable security checks on the local port via the previously added SPFSR register.
When security checks are enabled, an incoming packet will trigger an FDB lookup with the packet's source MAC and the FID it was classified to. If an FDB entry was not found or was found to be pointing to a different port, the packet will be dropped. Such packets increment the "discard_ingress_general" ethtool counter. For added visibility, user space can trap such packets to the CPU by enabling the "locked_port" trap. Example:
# devlink trap set pci/0000:06:00.0 trap locked_port action trap
Unlike other configurations done via bridge port flags (e.g., learning, flooding), security checks are enabled in the device on a per-port basis and not on a per-{port, VLAN} basis. As such, scenarios where user space can configure different locking settings for different VLANs configured on a port need to be vetoed. To that end, veto the following scenarios:
1. Locking is set on a bridge port that is a VLAN upper
2. Locking is set on a bridge port that has VLAN uppers
3. VLAN upper is configured on a locked bridge port
Examples:
# bridge link set dev swp1.10 locked on Error: mlxsw_spectrum: Locked flag cannot be set on a VLAN upper.
# ip link add link swp1 name swp1.10 type vlan id 10 # bridge link set dev swp1 locked on Error: mlxsw_spectrum: Locked flag cannot be set on a bridge port that has VLAN uppers.
# bridge link set dev swp1 locked on # ip link add link swp1 name swp1.10 type vlan id 10 Error: mlxsw_spectrum: VLAN uppers are not supported on a locked port.
Signed-off-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
136b8dfb |
| 08-Nov-2022 |
Ido Schimmel <idosch@nvidia.com> |
mlxsw: spectrum_switchdev: Use extack in bridge port flag validation
Propagate extack to mlxsw_sp_port_attr_br_pre_flags_set() in order to communicate error messages related to bridge port flag vali
mlxsw: spectrum_switchdev: Use extack in bridge port flag validation
Propagate extack to mlxsw_sp_port_attr_br_pre_flags_set() in order to communicate error messages related to bridge port flag validation.
Example:
# bridge link set dev swp1 locked on Error: mlxsw_spectrum: Unsupported bridge port flag.
More error messages will be added in subsequent patches.
Signed-off-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
5a660e43 |
| 08-Nov-2022 |
Ido Schimmel <idosch@nvidia.com> |
mlxsw: spectrum_switchdev: Add support for locked FDB notifications
In Spectrum, learning happens in parallel to the security checks. Therefore, regardless of the result of the security checks, a le
mlxsw: spectrum_switchdev: Add support for locked FDB notifications
In Spectrum, learning happens in parallel to the security checks. Therefore, regardless of the result of the security checks, a learning notification will be generated by the device and polled later on by the driver.
Currently, the driver reacts to learning notifications by programming corresponding FDB entries to the device. When a port is locked (i.e., has security checks enabled), this can no longer happen, as otherwise any host will blindly gain authorization.
Instead, notify the learned entry as a locked entry to the bridge driver that will in turn notify it to user space, in case MAB is enabled. User space can then decide to authorize the host by clearing the "locked" flag, which will cause the entry to be programmed to the device.
Signed-off-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
b72cb660 |
| 08-Nov-2022 |
Ido Schimmel <idosch@nvidia.com> |
mlxsw: spectrum_switchdev: Prepare for locked FDB notifications
Subsequent patches will need to report locked FDB entries to the bridge driver. Prepare for that by adding a 'locked' argument to mlxs
mlxsw: spectrum_switchdev: Prepare for locked FDB notifications
Subsequent patches will need to report locked FDB entries to the bridge driver. Prepare for that by adding a 'locked' argument to mlxsw_sp_fdb_call_notifiers() according to which the 'locked' bit is set in the FDB notification info. For now, always pass 'false'.
Signed-off-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
77b7f83d |
| 04-Jul-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: Enable unified bridge model
After all the preparations for unified bridge model, finally flip mlxsw driver to use the new model.
Change config profile, set 'ubridge' to true and remove the c
mlxsw: Enable unified bridge model
After all the preparations for unified bridge model, finally flip mlxsw driver to use the new model.
Change config profile, set 'ubridge' to true and remove the configurations that are relevant only for the legacy model. Set 'flood_mode' to 'controlled' as the current mode is not supported with unified bridge model.
Remove all the code which is dedicated to the legacy model. Remove 'struct mlxsw_sp.ubridge' variable which was temporarily added to separate configurations between the models.
Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
53d7ae53 |
| 04-Jul-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: Configure egress VID for unicast FDB entries
Using unified bridge model, firmware no longer configures the egress VID "under the hood" and moves this responsibility to software.
For layer 2,
mlxsw: Configure egress VID for unicast FDB entries
Using unified bridge model, firmware no longer configures the egress VID "under the hood" and moves this responsibility to software.
For layer 2, this means that software needs to determine the egress VID for both unicast (i.e., FDB) and multicast (i.e., MDB and flooding) flows.
Unicast FDB records and unicast LAG FDB records have new fields - "set_vid" and "vid", set them. For records which point to router port, do not set these fields.
Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
e28cd993 |
| 29-Jun-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: spectrum_switchdev: Convert MDB code to use PGT APIs
The previous patches added common APIs for maintaining PGT (Port Group Table) table. In the legacy model, software did not interact with t
mlxsw: spectrum_switchdev: Convert MDB code to use PGT APIs
The previous patches added common APIs for maintaining PGT (Port Group Table) table. In the legacy model, software did not interact with this table directly. Instead, it was accessed by firmware in response to registers such as SFTR and SMID. In the new model, software has full control over the PGT table using the SMID register.
The configuration of MDB entries is already done via SMID, so the new PGT APIs can be used also using the legacy model, the only difference is that MID index should be aligned to bridge model. See a previous patch which added API for that.
The main changes are: - MDB code does not maintain bitmap of ports in MDB entry anymore, instead, it stores a list of ports with additional information. - MDB code does not configure SMID register directly anymore, it will be done via PGT API when port is first added or removed. - Today MDB code does not update SMID when port is added/removed while multicast is disabled. Instead, it maintains bitmap of ports and once multicast is enabled, it rewrite the entry to hardware. Using PGT APIs, the entry will be updated also when multicast is disabled, but the mapping between {MAC, FID}->{MID} will not appear in SFD register. It means that SMID will be updated all the time and disable/enable multicast will impact only SFD configuration. - For multicast router, today only SMID is updated and the bitmap is not updated. Using the new list of ports, there is a reference count for each port, so it can be saved in software also. For such port, 'struct mlxsw_sp_mdb_entry.ports_count' will not be updated and the port in the list will be marked as 'mrouter'. - Finally, `struct mlxsw_sp_mid.in_hw` is not needed anymore.
Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
4c3f7442 |
| 29-Jun-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: spectrum_switchdev: Flush port from MDB entries according to FID index
Currently, flushing port from all MDB entries is done when the last VLAN is removed. This behavior is inaccurate, as por
mlxsw: spectrum_switchdev: Flush port from MDB entries according to FID index
Currently, flushing port from all MDB entries is done when the last VLAN is removed. This behavior is inaccurate, as port can be removed while there is another port which uses the same VLAN, in such case, this is not the last port which uses this VLAN and removed, but this port is supposed to be removed from the MDB entries.
Flush the port from MDB when it is removed, regardless the state of other ports. Flush only the MDB entries which are relevant for the same FID index.
Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
7434ed61 |
| 29-Jun-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: spectrum_switchdev: Add support for getting and putting MDB entry
A previous patch added support for init() and fini() for MDB entries. MDB entry can be updated, ports can be added and remove
mlxsw: spectrum_switchdev: Add support for getting and putting MDB entry
A previous patch added support for init() and fini() for MDB entries. MDB entry can be updated, ports can be added and removed from the entry. Add get() and put() functions, the first one checks if the entry already exists and otherwise initializes the entry. The second removes the entry just in case that there are no more ports in this entry.
Use the list of the ports which was added in a previous patch. When the list contains only one port which is not multicast router, and this port is removed, the MDB entry can be removed. Use 'struct mlxsw_sp_mdb_entry.ports_count' to know how many ports use the entry, regardless the use of multicast router ports.
When mlxsw_sp_mc_mdb_entry_put() is called with specific port which supposed to be removed, check if the removal will cause a deletion of the entry. If this is the case, call mlxsw_sp_mc_mdb_entry_fini() which first deletes the MDB entry and then releases the PGT entry, to avoid a temporary situation in which the MDB entry points to an empty PGT entry, as otherwise packets will be temporarily dropped instead of being flooded.
The new functions will be used in the next patches.
Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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ea0f58d6 |
| 29-Jun-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: spectrum_switchdev: Implement mlxsw_sp_mc_mdb_entry_{init, fini}()
The next patches will convert MDB code to use PGT APIs. The change will move the responsibility of allocating MID indexes an
mlxsw: spectrum_switchdev: Implement mlxsw_sp_mc_mdb_entry_{init, fini}()
The next patches will convert MDB code to use PGT APIs. The change will move the responsibility of allocating MID indexes and writing PGT configurations to hardware to PGT code. As part of this change, most of the MDB code will be changed and improved.
As a preparation for the above mentioned change, implement mlxsw_sp_mc_mdb_entry_{init, fini}(). Currently, there is a function __mlxsw_sp_mc_alloc(), which does not only allocate MID. In addition, there is no an equivalent function to free the MID. When mlxsw_sp_port_remove_from_mid() removes the last port, it handles MID removal. Instead, add init() and fini() functions, which use PGT APIs.
The differences between the existing and the new functions are as follows: 1. Today MDB code does not update SMID when port is added/removed while multicast is disabled. It maintains a bitmap of ports and once multicast is enabled, it writes the entry to hardware. Instead, using PGT APIs, the entry will be updated also when multicast is disabled, but the mapping between {MAC, FID}->{MID} (is configured using SFD) will be updated according to multicast state. It means that SMID will be updated all the time and disable/enable multicast will impact only SFD configuration.
2. Today the allocation of MID index is done as part of mlxsw_sp_mc_write_mdb_entry(). The fact that the entry will be written in hardware all the time, moves the allocation of the index to be as part of the MDB entry initialization. PGT API is used for the allocation.
3. Today the update of multicast router ports is done as part of mlxsw_sp_mc_write_mdb_entry(). Instead, add functions to add/remove all multicast router ports when entry is first added or removed. When new multicast router port will be added/removed, the dedicated API will be used to add/remove it from the existing entries.
4. A list of ports will be stored per MDB entry instead of the exiting bitmap. The list will contain the multicast router ports and maintain reference counter per port.
Add mlxsw_sp_mdb_entry_write() which is almost identical to mlxsw_sp_port_mdb_op(). Use more clear name and align the MID index to bridge model using PGT API. The existing function will be removed in the next patches.
Note that PGT APIs configure the firmware using SMID register, like the driver already does today for MDB entries, so PGT APIs can be used also using legacy bridge model.
Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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d2994e13 |
| 29-Jun-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: spectrum_switchdev: Add support for maintaining list of ports per MDB entry
As part of converting MDB code to use PGT APIs, PGT code stores which ports are mapped to each PGT entry. PGT code
mlxsw: spectrum_switchdev: Add support for maintaining list of ports per MDB entry
As part of converting MDB code to use PGT APIs, PGT code stores which ports are mapped to each PGT entry. PGT code is not aware of the type of the port (multicast router or not), as it is not relevant there.
To be able to release an MDB entry when the there are no ports which are not multicast routers, the entry should be aware of the state of its ports. Add support for maintaining list of ports per MDB entry.
Each port will hold a reference count as multiple MDB entries can use the same hardware MDB entry. It occurs because MDB entries in the Linux bridge are keyed according to their multicast IP, when these entries are notified to device drivers via switchdev, the multicast IP is converted to a multicast MAC. This conversion might cause collisions, for example, ff0e::1 and ff0e:1234::1 are both mapped to the multicast MAC 33:33:00:00:00:01.
Multicast router port will take a reference once, and will be marked as 'mrouter', then when port in the list is multicast router and its reference value is one, it means that the entry can be removed in case that there are no other ports which are not multicast routers. For that, maintain a counter per MDB entry to count ports in the list, which were added to the multicast group, and not because they are multicast routers. When this counter is zero, the entry can be removed.
Add mlxsw_sp_mdb_entry_port_{get,put}() for regular ports and mlxsw_sp_mdb_entry_mrouter_port_{get,put}() for multicast router ports. Call PGT API to add or remove port from PGT entry when port is first added or removed, according to the reference counting.
Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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5d0512e5 |
| 29-Jun-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: spectrum_switchdev: Add support for maintaining hash table of MDB entries
Currently MDB entries are stored in a list as part of 'struct mlxsw_sp_bridge_device'. Storing them in a hash table i
mlxsw: spectrum_switchdev: Add support for maintaining hash table of MDB entries
Currently MDB entries are stored in a list as part of 'struct mlxsw_sp_bridge_device'. Storing them in a hash table in addition to the list will allow finding a specific entry more efficiently.
Add support for the required hash table, the next patches will insert and remove MDB entries from the table. The existing code which adds and removes entries will be removed and replaced by new code in the next patches, so there is no point to adjust the existing code.
Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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0ac98543 |
| 29-Jun-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: spectrum_switchdev: Save MAC and FID as a key in 'struct mlxsw_sp_mdb_entry'
The next patch will add support for storing all the MDB entries in a hash table. As a preparation, save the MAC ad
mlxsw: spectrum_switchdev: Save MAC and FID as a key in 'struct mlxsw_sp_mdb_entry'
The next patch will add support for storing all the MDB entries in a hash table. As a preparation, save the MAC address and the FID in a separate structure. This structure will be used later as a key for the hash table.
Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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eaa0791a |
| 29-Jun-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: spectrum_switchdev: Rename MIDs list
Currently, the list which stores the MDB entries for a given bridge instance is called 'mids_list'.
This name is not accurate as a MID entry stores a bit
mlxsw: spectrum_switchdev: Rename MIDs list
Currently, the list which stores the MDB entries for a given bridge instance is called 'mids_list'.
This name is not accurate as a MID entry stores a bitmap of ports to which a packet needs to be replicated and a MDB entry stores the mapping from {MAC, FID} to PGT index (MID)
Rename it to 'mdb_list'.
Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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eede53a4 |
| 29-Jun-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: spectrum_switchdev: Rename MID structure
Currently the structure which represents MDB entry is called 'struct mlxsw_sp_mid'. This name is not accurate as a MID entry stores a bitmap of ports
mlxsw: spectrum_switchdev: Rename MID structure
Currently the structure which represents MDB entry is called 'struct mlxsw_sp_mid'. This name is not accurate as a MID entry stores a bitmap of ports to which a packet needs to be replicated and a MDB entry stores the mapping from {MAC, FID} to PGT index (MID).
Rename the structure to 'struct mlxsw_sp_mdb_entry'. The structure 'mlxsw_sp_mid' is defined as part of spectrum.h. The only file which uses it is spectrum_switchdev.c, so there is no reason to expose it to other files. Move the definition to spectrum_switchdev.c.
Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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